Multiprocessor electronic circuit including a plurality of processors and electronic data processing system

• US 20090113212A1
• Filed: 10/09/2008
• Published: 04/30/2009
• Est. Priority Date: 10/30/2007
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Mayer, Ulrich, Swaney, Scott Barnett, Shum, Chung-Lung Kevin, Fuchs, Thomas, Koehler, Thomas
• Granted Patent: US 8,135,960 B2
• Time in Patent Office: Days
• US Class Current: 713/189
• CPC Class Codes: G06F 21/72 in cryptographic circuits

Abstract

A multiprocessor electronic circuit and an electronic data processing system comprising such circuit are disclosed for reducing the power consumption and the chip area consumption of a multiprocessor system having cryptographic functionality. In one embodiment, the multiprocessor electronic circuit comprises a plurality of processors, a single cryptographic processing unit that comprises a plurality of input/output buffer pairs and two cryptographic engines, a cipher engine and a hash engine, and associated control logic.

Claims

1. A multiprocessor electronic circuit comprising:

a plurality of processors;

a single cryptographic processing unit that comprises a plurality of input/output buffer pairs storing source data issued from and target data to be transmitted to the plurality of processors and that further comprises two cryptographic engines, a cipher engine and a hash engine, wherein the functional steps performed in either the cipher engine or the hash engine are performed independently from each other; and

a control logic that connects the cryptographic processing unit and the plurality of processors and that implements the functionality of temporarily assigning the cryptographic processing unit to one of the plurality of processors.

2. The multiprocessor electronic circuit according to claim 1, wherein the cryptographic processing unit performs a reset procedure independently of each of the plurality of processors.

3. The multiprocessor electronic circuit according to claim 1, wherein an indicator latch is implemented including a readline connected to one of the plurality of processors, allowing the processor to determine whether a required one of the cryptographic engines is currently busy working for another processor.

4. The multiprocessor electronic circuit according to claim 1, further including control logic for performing at least one of the following:

a functional reset of the cryptographic processing unit or one of the cryptographic engines,

error reporting,

a recovery/retry mechanism,

error reporting and handling for errors occurring during a transition of assignment of one of the cryptographic engines, and

error reporting handling due to a power save status of the cryptographic processing unit.

5. An electronic data processing system comprising a multiprocessor electronic circuit, the multiprocessor electronic circuit comprising:

a plurality of processors;

a single cryptographic processing unit that comprises a plurality of input/output buffer pairs storing source data issued from and target data to be transmitted to the plurality of processors and that further comprises two cryptographic engines, a cipher engine and a hash engine, wherein the functional steps performed in either the cipher engine or the hash engine are performed independently from each other; and

a control logic that connects the cryptographic processing unit and the plurality of processors and that implements the functionality of temporarily assigning the cryptographic processing unit to one of the plurality of processors.