METHODS FOR ANALYZING SCAN CHAINS, AND FOR DETERMINING NUMBERS OR LOCATIONS OF HOLD TIME FAULTS IN SCAN CHAINS

• US 20090113263A1
• Filed: 03/31/2008
• Published: 04/30/2009
• Est. Priority Date: 10/31/2007
• Status: Active Grant

• Current Assignee: Advantest Corporation
• Original Assignee: Verigy Limited (Advantest Corporation)
• Inventors: Winblad, Gary A., Cannon, Stephen A., Dokken, Richard C., Crouch, Alfred L.
• Granted Patent: US 8,010,856 B2
• Time in Patent Office: Days
• US Class Current: 714/726
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals

Abstract

In a method for determining a number of possible hold time faults in a scan chain of a DUT, an environmental variable of the scan chain is set to a value believed to cause a hold time fault in the scan chain, and then a pattern is shifted through the scan chain. The pattern has a background pattern of at least n contiguous bits of a first logic state, followed by at least one bit of a second logic state, where n is a length of the scan chain. The number of possible hold time faults in the scan chain can be determined as a difference between i) a clock cycle when the at least one bit is expected to cause a transition at an output of the scan chain, and ii) a clock cycle when the at least one bit actually causes a transition at the output of the scan chain. If a value of the environmental variable at which the scan chain operates correctly can be determined, the location of one or more hold time faults can also be determined.

Claims

1. A method for analyzing a scan chain of a device under test, comprising:

setting an environmental variable of the scan chain to a first value, and then shifting a non-constant sequence pattern through the scan chain to determine whether an unexpected toggle pattern is output from the scan chain;

setting the environmental variable to a second value, and then shifting the non-constant sequence pattern through the scan chain to determine whether the non-constant sequence pattern is output from the scan chain at an expected time; and

at least when the scan chain both i) outputs an unexpected toggle pattern at the first value of the environmental variable, and ii) fails to output the non-constant sequence pattern at the second value of the environmental variable, at the expected time, determining a number of possible hold time faults in the scan chain based on results of a first number of scan tests.

2. The method of claim 1, further comprising, when the scan chain both i) outputs an unexpected toggle pattern at the first value of the environmental variable, and ii) outputs the non-constant sequence pattern at the second value of the environmental variable, at the expected time, determining a location of at least one possible hold time fault in the scan chain based on results of a second number of scan tests, wherein the second number of scan tests are performed using the first and second values of the environmental variable.

3. The method of claim 2, wherein determining the location of at least one possible hold time fault in the scan chain comprises:

shifting at least one scan pattern into the scan chain while the environmental variable is set to the second value;

for each of the at least one scan pattern shifted into the scan chain, and after shifting a particular scan pattern into the scan chain,

temporarily setting the environmental variable to the first value; and

then

clocking the scan chain at least once; and

then

shifting the particular scan pattern out of the scan chain while the environmental variable is set to the second value;

on a per-bit basis, comparing each particular scan pattern shifted out of the scan chain to an expected scan pattern, to identify at least one location of a difference in bits; and

determining, based on the at least one location of the difference in bits, the location of the at least one possible hold time fault in the scan chain.

4. The method of claim 3, wherein shifting at least one scan pattern into the scan chain, when determining the location of at least one possible hold time fault in the scan chain, comprises:

shifting a plurality of scan patterns into the scan chain, the plurality of scan patterns having sequences of bits that ensure each scan cell'"'"'s experience of a logic zero-to-one, logic one-to-one, logic one-to-zero and logic zero-to-zero transition when the scan chain is clocked at the first value of the environmental variable, thereby enabling the location(s) of all possible hold time faults to be determined, regardless of polarity of the hold time fault(s).

5. The method of claim 4, wherein the plurality of scan patterns comprise patterns of repeating hexadecimal 3'"'"'s, 6'"'"'s, C'"'"'s and 9'"'"'s.

6. The method of claim 3, wherein clocking the scan chain at least once consists of clocking the scan chain only once.

7. The method of claim 1, further comprising, when the scan chain both i) outputs an unexpected toggle pattern at the first value of the environmental variable, and ii) outputs the non-constant sequence pattern at the second value of the environmental variable, determining a possible number of hold time faults in the scan chain based on results of a first number of scan tests.

8. The method of claim 1, further comprising, after shifting the non-constant sequence pattern through the scan chain at the first value of the environmental variable, i) identifying the scan chain as “

good”

when an expected pattern is output from the scan chain, and ii) identifying the scan chain as “

flat-lined”

when a flat-line pattern is output from the scan chain.

9. The method of claim 8, further comprising, only setting the environmental variable to the second value when the scan chain outputs an unexpected toggle pattern at the first value of the environmental variable.

10. The method of claim 1, further comprising, receiving the first and second values of the environmental value from a user.

11. The method of claim 1, further comprising, identifying the second value of the environmental variable by:

for each of a plurality of values of the environmental variable, shifting the non-constant sequence pattern through the scan chain to determine whether the non-constant sequence pattern is output from the scan chain at an expected time; and

identifying the second value of the environmental variable as one of the plurality of values that causes the non-constant sequence pattern to be output from the scan chain at the expected time.

12. The method of claim 1, wherein the first value is within a normal operating range of the environmental variable for the scan chain, and wherein the second value is outside a normal operating range of the environmental variable for the scan chain.

13. The method of claim 1, wherein determining the number of hold time faults in the scan chain comprises:

setting the environmental variable to the first value; and

then

shifting through the scan chain a background pattern of at least n contiguous bits of a first logic state, followed by at least one bit of a second logic state; and

determining the number of possible hold time faults in the scan chain as a difference between i) a clock cycle when the at least one bit is expected to cause a transition at an output of the scan chain, and ii) a clock cycle when the at least one bit actually causes a transition at the output of the scan chain.

14. The method of claim 1, wherein determining the number of hold time faults in the scan chain comprises:

setting the environmental variable to the first value; and

then

shifting through the scan chain a pattern of 2n bits of a first logic state, followed by 2n bits of a second logic state, followed by n bits of the first logic state, where n is the number of scan cells in the scan chain; and

determining a number of rising edge hold time faults, and a number of falling edge hold time faults, as differences between i) a clock cycle when a respective edge is expected to be output from the scan chain, and ii) a clock cycle when the respective edge is actually output from the scan chain.

15. The method of claim 1, wherein, if the scan chain has odd parity, determining whether a particular pattern is output from the scan chain comprises accounting for pattern inversion.

16. The method of claim 1, wherein the environmental variable is a supply voltage.

17. The method of claim 1, wherein the environmental variable is a temperature.

18. The method of claim 1, wherein the environmental variable is a scan shift clock rate.

19. A method for analyzing a scan chain of a device under test, comprising:

setting an environmental variable of the scan chain to a first value, and then shifting a non-constant sequence pattern through the scan chain to determine whether an unexpected toggle pattern is output from the scan chain;

setting the environmental variable to a second value, and then shifting the non-constant sequence pattern through the scan chain to determine whether the non-constant sequence pattern is output from the scan chain at an expected time; and

when the scan chain both i) outputs an unexpected toggle pattern at the first value of the environmental variable, and ii) outputs the non-constant sequence pattern at the second value of the environmental variable, at the expected time, determining a location of at least one possible hold time fault in the scan chain based on results of a number of scan tests, wherein the second number of scan tests are performed using the first and second values of the environmental variable.

20. The method of claim 19, wherein the environmental variable is a supply voltage.

21. A method for determining a number of possible hold time faults in a scan chain of a device under test, comprising:

setting an environmental variable of the scan chain to a value believed to cause a hold time fault in the scan chain; and

then

shifting a pattern through the scan chain, the pattern having a background pattern of at least n contiguous bits of a first logic state, followed by at least one bit of a second logic state, where n is a length of the scan chain; and

determining the number of possible hold time faults in the scan chain as a difference between i) a clock cycle when the at least one bit is expected to cause a transition at an output of the scan chain, and ii) a clock cycle when the at least one bit actually causes a transition at the output of the scan chain.

22. The method of claim 21, wherein:

the pattern shifted through the scan chain comprises 2n bits of the first logic state, followed by 2n bits of the second logic state, followed by n bits of the first logic state; and

determining the number of hold time faults in the scan chain comprises determining a number of rising edge hold time faults, and a number of falling edge hold time faults, as differences between i) a clock cycle when a respective edge is expected to be output from the scan chain, and ii) a clock cycle when the respective edge is actually output from the scan chain.

23. The method of claim 21, wherein the environmental variable is a supply voltage.

24. A method for determining a location of at least one possible hold time fault in a scan chain of a device under test, comprising:

alternately setting an environmental variable of the scan chain to a first value and a second value, the first value believed to cause a hold time fault in the scan chain, and the second value believed not to cause a hold time fault in the scan chain;

shifting at least one scan pattern into the scan chain while the environmental variable is set to the second value;

for each scan pattern shifted into the scan chain, and after shifting a particular scan pattern into the scan chain,

temporarily setting the environmental variable to the first value; and

then

clocking the scan chain at least once; and

then

shifting the particular scan pattern out of the scan chain while the environmental variable is set to the second value;

on a per-bit basis, comparing each particular scan pattern shifted out of the scan chain to an expected scan pattern, to identify at least one location of a difference in bits; and

determining, based on the at least one location of the difference in bits, a location of the at least one possible hold time fault in the scan chain.

25. The method of claim 24, wherein shifting at least one scan pattern into the scan chain comprises:

shifting a plurality of scan patterns into the scan chain, the plurality of scan patterns having sequences of bits that ensure each scan cell'"'"'s experience of a logic zero-to-one, logic one-to-one, logic one-to-zero and logic zero-to-zero transition when the scan chain is clocked at the first value of the environmental variable, thereby enabling the location(s) of all possible hold time faults to be determined, regardless of polarity of the hold time fault(s).

26. The method of claim 25, wherein the plurality of scan patterns comprise patterns of repeating hexadecimal 3'"'"'s, 6'"'"'s, C'"'"'s and 9'"'"'s.

27. The method of claim 24, wherein clocking the scan chain at least once consists of clocking the scan chain only once.

28. The method of claim 24, wherein the environmental variable is a supply voltage.