ERROR CORRECTION CODING IN FLASH MEMORY DEVICES

• US 20090113272A1
• Filed: 10/30/2007
• Published: 04/30/2009
• Est. Priority Date: 10/30/2007
• Status: Active Grant

• Current Assignee: Infineon Technologies Batam PT (Infineon Technologies AG)
• Original Assignee: Spansion LLC (Infineon Technologies AG)
• Inventors: Tan, Tat Hin, Hancock, Bryan W., Bautista, Ed, Parker, Allan, Huang, Jackson
• Granted Patent: US 8,239,732 B2
• Time in Patent Office: Days
• US Class Current: 714/765
• CPC Class Codes: G06F 11/1052 Bypassing or disabling error detection or correction

Abstract

Systems and/or methods that facilitate error correction of data are presented. An error correction code (ECC) control component facilitates enabling or disabling error correction of data being written to or read from memory, such as flash memory, based on ECC indicator data associated with a piece of data. The ECC control component can analyze data, parity code, and/or indicator data associated with the incoming data and/or data stored in the memory location where the incoming data is to be written to determine whether parity code can be written for the incoming data and/or whether error correction can be enabled with respect to the incoming data. Error correction can be enabled when an indicator bit associated with the data is unprogrammed (e.g., bit set to ‘1’ state) and can be disabled by programming the indicator bit (e.g., bit set to a ‘0’ state).

Claims

1. A system that facilitates error correction of data in a memory, comprising:

an error correction code (ECC) control component that at least one of enables or disables error correction based on indicator data to facilitate error correction of data associated with the memory; and

the memory that includes a plurality of memory locations, wherein at least one of data, parity code, or indicator data, or a combination thereof, is written to, read from, or stored in, at least one memory location of the plurality of the memory locations.

2. The system of claim 1, the memory is comprised of at least one of a NOR flash memory or a NAND flash memory, or a combination thereof.

3. The system of claim 1, the indicator data is comprised of at least one indicator bit, the ECC control component allows the at least one indicator bit to remain unprogrammed to enable error correction of data associated with the at least one indicator bit and facilitates a program of the at least one indicator bit to disable error correction of the data associated with the at least one indicator bit.

4. The system of claim 3, during a read operation, the ECC control component analyzes at least one of the data, the parity code, or the indicator data, or a combination thereof, and enables error correction of the data when the at least one indicator bit is unprogrammed and disables error correction of the data when the at least one indicator bit is programmed.

5. The system of claim 3, during a write buffer program operation, the ECC control component analyzes at least one of data, parity code, or indicator data, or a combination thereof, associated with a memory location in which data associated with the write buffer program operation is to be stored, and enables error correction of the data when the at least one indicator bit is unprogrammed and bits associated with the parity code are all unprogrammed, and disables error correction of the data when the at least one indicator bit is programmed or at least one bit associated with the parity code is programmed.

6. The system of claim 1, further comprising a program component that facilitates at least one of write buffer program of data or word/byte program of data, or a combination thereof, the program component aligns data into data chunks of a predetermined number of bits when data is programmed in a write buffer program mode.

7. The system of claim 6, the ECC control component disables error correction when the program component is in a word/byte program mode.

8. The system of claim 1, the ECC control component enables error correction associated with a memory location that is erased.

9. The system of claim 1, further comprising:

a host processor that facilitates execution of operations on data; and

a cryptographic component receives data from at least one of the host processor or the memory, or a combination thereof, the cryptographic component facilitates at least one of encryption or decryption of the data.

10. An electronic device comprising the system of claim 1, the electronic device is one of a computer, a cellular phone, a digital phone, a video device, a smart card, a personal digital assistant, a television, an electronic game, a digital camera, an electronic organizer, an audio player, an audio recorder, an electronic device associated with digital rights management, a Personal Computer Memory Card International Association (PCMCIA) card, a trusted platform module (TPM), an electronic control unit associated with motor vehicles, a global positioning satellite (GPS) unit, an electronic device associated with an airplane, an electronic device associated with an industrial control system, a Hardware Security Module (HSM), a set-top box, a secure memory device with computational capabilities, or an electronic device with a tamper-resistant chip.

11. A method that facilitates error correction of data, comprising:

executing an operation in a memory associated with the data, the operation is at least one of a read, a program, a write buffer program, a word/byte program, or an erase; and

at least one of enabling error correction or disabling error correction of the data based on a value of indicator data associated with the data.

13. The method of claim 11, further comprising:

selecting a word/byte programming mode;

generating a word/byte operation that specifies a memory location in the memory to which data is to be written;

programming the data associated with the word/byte operation in the memory location;

automatically programming an indicator bit associated with the memory location; and

disabling error correction with regard to the data.

14. The method of claim 11, further comprising:

aligning data into data chunks of a predetermined number of bits, the operation is a write buffer program operation;

reading at least one of data, parity data, or indicator data, or a combination thereof, associated with a memory location in the memory specified by the write buffer program operation;

analyzing the at least one of data, parity data, or indicator data, or a combination thereof,

determining at least one of enabling error correction or disabling error correction based on at least one of the parity data or the indicator data, or a combination thereof

15. The method of claim 14, further comprising:

enabling error correction associated with the data that is associated with the write buffer program operation, wherein the parity data and the indicator data associated with the memory location are unprogrammed and error correction is enabled with regard to the memory location;

generating parity data associated with the data that is associated with the write buffer program operation;

programming the data and the parity data associated with the write buffer program operation into the memory location.

16. The method of claim 15, further comprising:

determining if a programming failure occurred;

determining if the programming error occurred in the data when it is determined that a programming failure occurred;

determining if the programming error occurred in the parity data when it is determined that a programming failure occurred;

programming an indicator bit associated with the indicator data when a programming failure occurs if it is determined that the programming failure is based on an error associated with the programming of the parity data, and there is no error related to the programming of the data;

disabling error correction related to the data; and

programming the data into the memory location in the memory.

17. The method of claim 14, further comprising:

programming the indicator bit to disable error correction with regard to the data associated with the write buffer program operation, wherein at least one of a bit associated with the parity data that is associated with the memory location or a bit associated with the indicator data that is associated with the memory location is programmed and error correction is disabled with regard to the memory location; and

programming the data associated with the write buffer program operation into the memory location.

18. The method of claim 11, further comprising:

erasing a memory location in the memory, the operation is an erase operation;

enabling error correction with regard to the memory location.

12. The method of claim 12, further comprising:

generating a read operation that specifies a memory location in the memory;

reading at least one of data, parity data, and indicator data, or a combination thereof, from the memory location, the indicator data is comprised of an indicator bit;

determining if the indicator bit is programmed; and

at least one of;

disabling error correction of the data if the indicator bit is programmed, and providing the data, or

enabling error correction of the data if the indicator bit is unprogrammed, providing the data and the parity data for error correction, performing error correction of the data, and providing the data after error correction is performed.

19. A system that facilitates error correction of data, comprising:

means for executing an operation related to data in a memory; and

means for at least one of enabling error correction or disabling error correction of the data based on a value of at least one indicator bit associated with the data.

20. The system of claim 19, further comprising:

means for analyzing at least one of data, parity code, or the at least one indicator bit, or a combination thereof,

means for performing error correction of the data;

means for encoding data; and

means for decoding data.