Design Structure for an Automated Real-Time Frequency Band Selection Circuit for use with a Voltage Controlled Oscillator

• US 20090113361A1
• Filed: 10/30/2007
• Published: 04/30/2009
• Est. Priority Date: 10/30/2007
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Malladi, Anjali R., Feng, Kai D.
• Granted Patent: US 7,675,367 B2
• Time in Patent Office: Days
• US Class Current: 716/106
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/113 using frequency discriminator

Abstract

A design structure for an integrated circuit including a phase-locked loop (PLL) circuit responsive to a voltage controlled oscillator (VCO) frequency band selection circuit that provides automatic frequency band selection in real time to account for run-time variations, such as power supply and temperature variations over time. The PLL includes a charge pump and an LC tank circuit that provides the automatic frequency band selection based on a VCO control voltage signal supplied by the charge pump.

Claims

1. A design structure embodied in a machine readable medium used in a design process for an integrated circuit, the design structure of said circuit comprising:

a phase-locked loop circuit that includes;

a charge pump outputting a control signal during operation of said phase-locked loop circuit;

a voltage controlled oscillator responsive to said control signal and to a tuning signal during operation of said phase-locked loop circuit; and

an LC tank circuit configured to generate said tuning signal as a function of said control signal, said LC tank circuit including;

control signal monitoring circuitry configured to automatically monitor said control signal and generate an output signal;

a controller for automatically generating a band selection signal as a function of said output signal;

band sliding circuitry for generating an output voltage in any one of a plurality of bands, said band sliding circuitry being configured to select said one of said plurality of bands as a function of said band selection signal; and

band determining circuitry responsive to said output voltage so as to create said tuning signal.

2. The design structure of claim 1, wherein the design structure comprises a netlist, which describes the circuit.

3. The design structure of claim 1, wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.

4. The design structure of claim 1, wherein the design structure includes at least one of test data files, characterization data, verification data, or design specifications.

5. A design structure embodied in a machine readable medium for performing a method of automatically selecting a frequency band within a phase-locked loop (PLL) during functional operation of the PLL, the PLL having a lock time, the design structure comprising:

a means for receiving a voltage control signal from the PLL;

a means for monitoring said voltage control signal relative to a range of acceptable values;

a means for generating a band selection signal as a function of said voltage control signal and said range of acceptable values;

a means for selecting a frequency band as a function of said band selection signal;

a means for providing a band update time greater than the lock time of the PLL; and

a means for determining an operational frequency band of the PLL in response to said frequency band selected as a function of said band selection signal.