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FILLER CELLS FOR DESIGN OPTIMIZATION IN A PLACE-AND-ROUTE SYSTEM

  • US 20090113368A1
  • Filed: 10/26/2007
  • Published: 04/30/2009
  • Est. Priority Date: 10/26/2007
  • Status: Active Grant
First Claim
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1. A method for laying out an integrated circuit design, for use with a database defining a plurality of filler cell designs, the layout being for use in fabricating an integrated circuit device according to the design, comprising the steps of:

  • providing a first layout of the integrated circuit design, the first layout defining a plurality of masks, the masks defining a plurality of integrated circuit features when applied in a fabrication process, the features defining a plurality of circuit layout cells having gaps therebetween; and

    inserting into each given gap in at least a subset of the gaps, a corresponding filler cell selected from the database in dependence upon a desired effect on a performance parameter of at least one circuit cell adjacent to the given gap.

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