FILLER CELLS FOR DESIGN OPTIMIZATION IN A PLACE-AND-ROUTE SYSTEM
First Claim
1. A method for laying out an integrated circuit design, for use with a database defining a plurality of filler cell designs, the layout being for use in fabricating an integrated circuit device according to the design, comprising the steps of:
- providing a first layout of the integrated circuit design, the first layout defining a plurality of masks, the masks defining a plurality of integrated circuit features when applied in a fabrication process, the features defining a plurality of circuit layout cells having gaps therebetween; and
inserting into each given gap in at least a subset of the gaps, a corresponding filler cell selected from the database in dependence upon a desired effect on a performance parameter of at least one circuit cell adjacent to the given gap.
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Accused Products
Abstract
A system and method are provided for laying out an integrated circuit design into a plurality of circuit layout cells having gaps therebetween, and inserting into each given one of at least a subset of the gaps, a corresponding filler cell selected from a predefined database in dependence upon a desired effect on a performance parameter of at least one circuit cell adjacent to the given gap. The circuit layout cells may be arranged in rows, and in some embodiments the selection of an appropriate filler cell for a given gap depends upon effects desired on a performance parameter of both circuit cells adjacent to the given gap. The predefined filler cells can include, for example, dummy diffusion regions, dummy poly lines, N-well boundary shifts and etch stop layer boundary shifts. In an embodiment, circuit layout cells can be moved in order to accommodate a selected filler cell.
57 Citations
21 Claims
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1. A method for laying out an integrated circuit design, for use with a database defining a plurality of filler cell designs, the layout being for use in fabricating an integrated circuit device according to the design, comprising the steps of:
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providing a first layout of the integrated circuit design, the first layout defining a plurality of masks, the masks defining a plurality of integrated circuit features when applied in a fabrication process, the features defining a plurality of circuit layout cells having gaps therebetween; and inserting into each given gap in at least a subset of the gaps, a corresponding filler cell selected from the database in dependence upon a desired effect on a performance parameter of at least one circuit cell adjacent to the given gap. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A system for laying out an integrated circuit design, for use with a database defining a plurality of filler cell designs, the layout being for use in fabricating an integrated circuit device according to the design, comprising:
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means for providing a first layout of the integrated circuit design, the first layout defining a plurality of masks, the masks defining a plurality of integrated circuit features when applied in a fabrication process, the features defining a plurality of circuit layout cells having gaps therebetween; and means for inserting into each given gap in at least a subset of the gaps, a corresponding filler cell selected from the database in dependence upon a desired effect on a performance parameter of at least one circuit cell adjacent to the given gap. - View Dependent Claims (20, 21)
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Specification