Layout designing method for semiconductor device and layout design supporting apparatus for the same

• US 20090113370A1
• Filed: 10/29/2008
• Published: 04/30/2009
• Est. Priority Date: 10/30/2007
• Status: Abandoned Application

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Yoshinaga, Hiroko
• Application Number:
  US12/289,490
• Publication Number:
  US 20090113370A1
• Time in Patent Office: Days
• US Class Current: 716/119
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

In a layout designing method of a semiconductor device, a first standard cell with a first well and a second standard cell with a second well are arranged. The first well and the second well are applied with different voltages, respectively. An empty cell is arranged in an area that a distance from the first well falls within a first distance. The second standard cell is moved such that the empty cell does not overlap with the empty cell, when the empty cell overlaps with the second well.

Claims

1. A layout designing method of a semiconductor device, comprising:

arranging a first standard cell with a first well and a second standard cell with a second well, wherein said first well and said second well are applied with different voltages, respectively;

arranging an empty cell in an area that a distance from said first well falls within a first distance; and

moving said second standard cell such that said empty cell does not overlap with said empty cell, when said empty cell overlaps with said second well.

2. The layout designing method according to claim 1, further comprising:

removing said empty cell after said moving.

3. The layout designing method according to claim 1, wherein said moving comprises:

setting inhibition of movement of said first standard cell; and

moving said second standard cell such that said empty cell and said second well do not overlap with each other, after said setting.

4. The layout designing method according to claim 1, further comprising:

determining a layout of a first power supply and a second power supply; and

connecting said first standard cell with said first power supply and said second standard cell with said second power supply.

5. The layout designing method according to claim 1, wherein said arranging a first standard cell and a second standard cell, comprises:

arranging a plurality of said first standard cells and a plurality of said second standard cells,

wherein said layout designing method further comprises;

re-arranging said plurality of first standard cells such that said plurality of first standard cells are collectively arranged, and

said arranging the empty cell is carried out after said re-arranging.

6. The layout designing method according to claim 5, further comprising:

determining a movable destination area to which said first standard cells can be moved,

wherein said re-arranging comprises;

collectively arranging said first standard cells by moving said first standard cells to said removable destination area.

7. A layout design supporting apparatus for a semiconductor device, comprising:

a first arranging section configured to arrange a first standard cell with a first well and a second standard cells with a second well, to generate an arranged layout data, wherein different voltages are applied to said first and second wells, respectively;

an empty cell arranging section configured to arrange an empty cell in an area within a first distance from said first well, to generate an empty cell arranged layout data; and

a second arranging section configured to re-arrange said second standard cell such that said empty cell and said second well do not overlap, when said empty cell overlaps with said second standard cell in the empty cell arranged layout data.

8. The layout design supporting apparatus according to claim 7, further comprising:

an empty cell removing section configured to remove said empty cell from the re-arranged layout data, to generate an empty cell removed layout data.

9. The layout design supporting apparatus according to claim 7, wherein said second arranging section comprises:

an inhibition setting section configured to set to inhibit said first standard cell from being moved; and

a second automatic arranging section configured to move said second standard cell for said empty cell not to overlap with said second well.

10. The layout design supporting apparatus according to claim 7, further comprising:

a power supply arranging section configured to determine a layout of a first power supply and a second power supply; and

a power supply interconnection section configured to interconnect said first standard cell with said first power supply and said second standard cell with said second power supply based on said empty cell removed layout data.

11. The layout design supporting apparatus according to claim 7, wherein said first arranging section arranges a plurality of said first standard cells and a plurality of said second standard cells, and

said layout design supporting apparatus further comprises:

a third arranging section configured to re-arrange said plurality of first standard cells in the arranged layout data such that said plurality of first standard cells are collectively located, to generate a re-arranged layout data, and

said empty cell arranging section arranges the empty cell in said re-arranged layout data.

12. The layout design supporting apparatus according to claim 11, further comprising:

a movable area setting section configured to set a movable destination area to which said first standard cell can be moved,

wherein said third arranging section moves said plurality of first standard cells into said movable destination area to collectively arrange said plurality of first standard cells.

13. A computer-readable recording medium in which a computer-readable program code is stored for realizing a layout designing method of a semiconductor device, said layout designing method comprising:

arranging a first standard cell with a first well and a second standard cell with a second well, wherein said first well and said second well are applied with different voltages, respectively;

arranging an empty cell in an area that a distance from said first well falls within a first distance; and

moving said second standard cell such that said empty cell does not overlap with said empty cell, when said empty cell overlaps with said second well.

14. The computer-readable recording medium according to claim 13, wherein said layout designing method further comprises:

removing said empty cell after said moving.

15. The computer-readable recording medium according to claim 13, wherein said moving comprises:

setting inhibition of movement of said first standard cell; and

moving said second standard cell such that said empty cell and said second well do not overlap with each other, after said setting.

16. The computer-readable recording medium according to claim 13, wherein said layout designing method further comprises:

determining a layout of a first power supply and a second power supply; and

connecting said first standard cell with said first power supply and said second standard cell with said second power supply.

17. The computer-readable recording medium according to claim 13, wherein said arranging a first standard cell and a second standard cell, comprises:

arranging a plurality of said first standard cells and a plurality of said second standard cells,

wherein said layout designing method further comprises;

re-arranging said plurality of first standard cells such that said plurality of first standard cells are collectively arranged, and

said arranging the empty cell is carried out after said re-arranging.

18. The computer-readable recording medium according to claim 17, wherein said layout designing method further comprises:

determining a movable destination area to which said first standard cells can be moved,

wherein said re-arranging comprises;

collectively arranging said first standard cells by moving said first standard cells to said removable destination area.