Layout design apparatus, layout design method, and computer product

• US 20090113373A1
• Filed: 08/22/2008
• Published: 04/30/2009
• Est. Priority Date: 10/31/2007
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Fukuda, Daisuke
• Granted Patent: US 8,104,008 B2
• Time in Patent Office: Days
• US Class Current: 716/129
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: Y02P 90/02 Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Abstract

A layout design apparatus that limits the maximum wiring density and the maximum edge length of partial regions when determining wiring layout. After determining the wiring layout, the layout design apparatus inserts a dummy into a partial region having a low wiring density and thereby, the minimum wiring density and the minimum edge length of the partial regions are limited. Thus, the respective wiring densities and respective edge lengths of the partial regions are constrained within a constant range and irregularities in the substrate surface after polishing can be suppressed.

Claims

1. A computer-readable recording medium storing therein a layout design program that, with respect to a target circuit to be designed and having a layout region partitioned into plural partial regions, causes a computer to execute:

searching for a wiring path between cells arranged in the layout region, based on a wire edge length of each of the partial regions; and

outputting a search result of the searching.

2. The according to claim 1, wherein the layout design program further causes the computer to execute:

acquiring, when the wiring path up to a given partial region is found as a result of the searching, the wire edge length of a partial region adjacent to the given partial region and exclusive of the partial regions through which the wiring path, found as a result of the searching, passes; and

determining, based on an acquisition result of the acquiring, a partial region to which the wiring path is to be searched for from the given partial region.

3. The computer-readable recording medium according to claim 2,

wherein the determining includes determining the partial region having the smallest wire edge length acquired at acquiring as the partial region to which the wiring path is to be searched from the given partial region.

4. The computer-readable recording medium according to claim 2, wherein

the acquiring includes acquiring, as a plurality of wiring path candidates, a plurality of wiring paths searched for based on a design rule, and

the determining includes determining as the wiring path, a wiring path candidate having, over the partial regions through which the wiring path candidate passes, the wire edge length that is smallest among the wiring path candidates.

5. The computer-readable recording medium according claim 1,

wherein the searching includes searching for the wiring path based on a wiring density of each of the partial regions.

6. The computer-readable recording medium according claim 1, wherein the layout design program further causes the computer to execute:

calculating a wiring density and the edge length of each of the partial regions through which the wiring path, found as a result of the searching, passes;

judging, based on the wiring density calculated at the calculating, whether the wiring density of a partial region is less than a wiring density limit; and

inserting a dummy into an unoccupied space of the partial region that is judged, at the judging, to have the wiring density less than the wiring density limit, and

the outputting includes outputting an insertion result concerning insertion of the dummy at the inserting.

7. The computer-readable recording medium according to claim 6, wherein

the judging includes judging whether the edge length of the partial region that is judged to have the wiring density less than the wiring density limit, is smaller than an edge length limit to obtain a judgment result;

the calculating includes calculating dimensions for the dummy based on the judgment result; and

the inserting includes inserting the dummy having the dimensions calculated at the calculating based on the judgment result.

8. The computer-readable recording medium according to claim 7,

wherein the calculating includes calculating the dimensions for the dummy based on the edge length of the partial region that is judged to have the wiring density less than the wiring density limit and the edge length smaller than the edge length limit.

9. The computer-readable recording medium according to claim 7,

wherein the calculating includes calculating dimensions for the dummy based on the wiring density of the partial region that is judged to have the wiring density less than the wiring density limit.

10. The computer-readable recording medium according to claim 6, wherein the layout design program further causes the computer to execute:

receiving a specification of the dimensions for the dummy, and

the judging includes judging whether the wiring density of the partial region is less than the wiring density limit subsequent to the insertion of the dummy, and

the inserting includes inserting a dummy having the dimensions specified at the specifying when at the judging it is judged that the wiring density is less than the limit value to replace the dummy inserted.

11. A layout design apparatus comprising:

a searching unit that, with respect to a target circuit to be designed and having a layout region partitioned into plural partial regions, searches for, based on a wire edge length of each of the partial regions, a wiring path between cells arranged in the layout region; and

an output unit that outputs a search result of the searching unit.

12. A layout design method, with respect to a target circuit to be designed and having a layout region partitioned into plural partial regions, comprising:

searching for, based on a wire edge length of each of the partial regions, a wiring path between cells arranged in the layout region; and

outputting a search result of the searching.