Integrated Circuit Embedded With Non-Volatile One-Time-Programmable And Multiple-Time Programmable Memory
First Claim
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1. A programmable non-volatile device situated on a substrate comprising:
- a floating gate;
wherein said floating gate is comprised of a material that is also used as a gate for a transistor device also situated on the substrate and associated with a logic gate and/or a volatile memory;
a source region; and
a drain region; and
an n-type channel coupling said source region and drain region;
wherein the drain region overlaps a sufficient portion of said gate such that a programming voltage for the device applied to said drain can be imparted to said floating gate through capacitive coupling.
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Abstract
A programmable non-volatile device uses a floating gate that functions as a FET gate that overlaps a portion of a source/drain region. This allows a programming voltage for the device to be imparted to the floating gate through capacitive coupling, thus changing the state of the device. The invention can be used in environments such as data encryption, reference trimming, manufacturing ID, security ID, and many other applications.
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Citations
22 Claims
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1. A programmable non-volatile device situated on a substrate comprising:
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a floating gate; wherein said floating gate is comprised of a material that is also used as a gate for a transistor device also situated on the substrate and associated with a logic gate and/or a volatile memory; a source region; and a drain region; and an n-type channel coupling said source region and drain region; wherein the drain region overlaps a sufficient portion of said gate such that a programming voltage for the device applied to said drain can be imparted to said floating gate through capacitive coupling. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A programmable device situated on a substrate comprising:
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a floating gate;
said floating gate being comprised of a material that includes impurities acting as charge storage sites and is also used as an insulating layer for other non-programmable devices situated on the substrate;a source region; and a drain region; and an n-type channel coupling said source region and drain region; wherein the drain region overlaps a sufficient portion of said gate such that a programming voltage applied to said drain can be imparted to said floating gate through capacitive coupling.
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19. A one-time programmable (OTP) device situated on a substrate comprising:
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a floating gate; wherein said floating gate is comprised of a material that is also shared by an interconnect and/or another gate for a transistor device also situated on the substrate and associated with a logic gate and/or a volatile memory; a source region; and a drain region overlapping a portion of said floating gate and capacitively coupled thereto; and an n-type channel coupling said source region and drain region; wherein a threshold of said floating gate can be permanently altered by channel hot electrons to store data in the OTP device.
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20. A one-time programmable (OTP) memory device incorporated on a silicon substrate with one or more other additional logic and/or non-OTP memory devices, characterized in that:
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a. said OTP memory device has an n-type channel; b. any and all regions and structures of said OTP memory device are derived solely from corresponding regions and structures used as components of the additional logic and/or non-OTP memory devices.
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21. A programmable memory device with a gate, an n-type impurity source and an n-type impurity drain on a silicon substrate comprising:
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an n-type channel; and wherein the n-type impurity drain overlaps a sufficient portion of said gate such that a programming voltage applied to said n-type impurity drain can be imparted to said gate through capacitive coupling; said gate being adapted to function as a floating gate so that the device has a programmed state defined by an amount of charge stored on said gate by said programming voltage; further wherein said charge on said floating gate can be erased so as to permit the device to be re-programmed.
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22. A one-time programmable (OTP) memory device with a gate, an n-type impurity source and an n-type impurity drain on a silicon substrate comprising:
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an n-type channel; and wherein the n-type impurity drain overlaps a sufficient portion of said gate such that a voltage applied to said n-type impurity drain can be imparted to said gate through capacitive coupling; said gate being adapted so that the OTP device has a programmed state defined by a charge state of said gate.
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Specification