Integrated Circuit Embedded With Non-Volatile One-Time-Programmable And Multiple-Time Programmable Memory

• US 20090114972A1
• Filed: 11/03/2008
• Published: 05/07/2009
• Est. Priority Date: 11/01/2007
• Status: Active Grant

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Original Assignee: Jonker LLC
• Inventors: Liu, David K.Y.
• Granted Patent: US 7,782,668 B2
• Time in Patent Office: Days
• US Class Current: 257/315
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 2216/10 Floating gate memory cells with a single polysilicon layer
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/60 the control gate being a doped region, e.g. single-poly memory cell

Abstract

A programmable non-volatile device uses a floating gate that functions as a FET gate that overlaps a portion of a source/drain region. This allows a programming voltage for the device to be imparted to the floating gate through capacitive coupling, thus changing the state of the device. The invention can be used in environments such as data encryption, reference trimming, manufacturing ID, security ID, and many other applications.

Claims

1. A programmable non-volatile device situated on a substrate comprising:

a floating gate;

wherein said floating gate is comprised of a material that is also used as a gate for a transistor device also situated on the substrate and associated with a logic gate and/or a volatile memory;

a source region; and

a drain region; and

an n-type channel coupling said source region and drain region;

wherein the drain region overlaps a sufficient portion of said gate such that a programming voltage for the device applied to said drain can be imparted to said floating gate through capacitive coupling.

2. The programmable device of claim 1 wherein said programming voltage is greater than 5 volts.

3. The programmable device of claim 1 wherein said floating gate can be erased.

4. The programmable device of claim 3 wherein said device can be re-programmed.

5. The programmable device of claim 3 wherein said floating gate is eraseable by an erase voltage applied to said source region.

6. The programmable device of claim 1 wherein a state of said floating gate can be determined by a read signal applied to said drain.

7. The programmable device of claim 1, wherein said read signal is less than about 1 volt.

8. The programmable device of claim 1 wherein said device is part of a programmable array embedded with separate logic circuits and/or memory circuits in an integrated circuit.

9. The programmable device of claim 8 wherein said device is associated with one of the following:

a data encryption circuit;

a reference trimming circuit;

a manufacturing ID; and

/or a security ID.

10. The programmable device of claim 1, wherein said capacitive coupling takes place in a first trench situated in the substrate.

11. The programmable device of claim 10, wherein a set of second trenches in said substrate are used as embedded DRAM.

12. The programmable device of claim 11, further including a second programmable device coupled in a paired latch arrangement such that a datum and its complement are stored in said paired latch.

13. The programmable device of claim 1, wherein a threshold voltage of said device can be set to multiple discrete levels.

14. The programmable device of claim 1, wherein said floating gate is a multi-level structure.

15. The programmable device of claim 1, wherein said device is part of a thin film transistor.

16. The programmable device of claim 1, wherein said floating gate is oriented in a non-planar configuration.

17. The programmable device of claim 1, wherein said floating gate is distributed and includes impurities acting as charge storage sites.

18. A programmable device situated on a substrate comprising:

a floating gate;

said floating gate being comprised of a material that includes impurities acting as charge storage sites and is also used as an insulating layer for other non-programmable devices situated on the substrate;

a source region; and

a drain region; and

an n-type channel coupling said source region and drain region;

wherein the drain region overlaps a sufficient portion of said gate such that a programming voltage applied to said drain can be imparted to said floating gate through capacitive coupling.

19. A one-time programmable (OTP) device situated on a substrate comprising:

a floating gate;

wherein said floating gate is comprised of a material that is also shared by an interconnect and/or another gate for a transistor device also situated on the substrate and associated with a logic gate and/or a volatile memory;

a source region; and

a drain region overlapping a portion of said floating gate and capacitively coupled thereto; and

an n-type channel coupling said source region and drain region;

wherein a threshold of said floating gate can be permanently altered by channel hot electrons to store data in the OTP device.

20. A one-time programmable (OTP) memory device incorporated on a silicon substrate with one or more other additional logic and/or non-OTP memory devices, characterized in that:

a. said OTP memory device has an n-type channel;

b. any and all regions and structures of said OTP memory device are derived solely from corresponding regions and structures used as components of the additional logic and/or non-OTP memory devices.

21. A programmable memory device with a gate, an n-type impurity source and an n-type impurity drain on a silicon substrate comprising:

an n-type channel; and

wherein the n-type impurity drain overlaps a sufficient portion of said gate such that a programming voltage applied to said n-type impurity drain can be imparted to said gate through capacitive coupling;

said gate being adapted to function as a floating gate so that the device has a programmed state defined by an amount of charge stored on said gate by said programming voltage;

further wherein said charge on said floating gate can be erased so as to permit the device to be re-programmed.

22. A one-time programmable (OTP) memory device with a gate, an n-type impurity source and an n-type impurity drain on a silicon substrate comprising:

an n-type channel; and

wherein the n-type impurity drain overlaps a sufficient portion of said gate such that a voltage applied to said n-type impurity drain can be imparted to said gate through capacitive coupling;

said gate being adapted so that the OTP device has a programmed state defined by a charge state of said gate.