SEMICONDUCTOR DEVICE

• US 20090115022A1
• Filed: 11/03/2008
• Published: 05/07/2009
• Est. Priority Date: 11/06/2007
• Status: Abandoned Application

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Takewaki, Toshiyuki, NAKASHIBA, Yasutaka
• Application Number:
  US12/263,650
• Publication Number:
  US 20090115022A1
• Time in Patent Office: Days
• US Class Current: 257/531
• CPC Class Codes: H01L 21/2855 by physical means, e.g. sputtering, evaporation H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/2885 using an external electrical current, i.e. electro-deposition
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device 1 includes: a copper interconnect layer 14 that has an interconnect containing an inductor 141, which is buried in an interconnect trench formed in an insulating layer 21; and copper interconnect layers 11 to 13, which include no inductor and are buried in interconnect trenches formed in other insulating layers 15, 17 and 19, respectively. An average grain size of the inductor 141 is larger than average grain sizes of the interconnects in the copper interconnect layers 11 to 13 that contain no inductor

Claims

1. A semiconductor device, comprising:

a first copper interconnect layer, having an interconnect including an inductor and buried in an interconnect trench formed in a first insulating layer; and

a second copper interconnect layer containing no inductor and buried in an interconnect trench formed in a second insulating layer, said second copper interconnect layer having a second interconnect, said first and second copper interconnect layers being stacked,

wherein an average grain size of said inductor is larger than an average grain size of said second interconnect of said second copper interconnect layer containing no inductor.

2. The semiconductor device as set forth in claim 1, wherein a linewidth of said inductor along a section perpendicular to an elongating orientation of said inductor is equal to or higher than 5 μ

m.

3. The semiconductor device as set forth in claim 1, wherein an aspect ratio presented by (the thickness of said inductor)/(the linewidth of said inductor) is equal to or lower than 0.2.

4. The semiconductor device as set forth in claim 1, wherein an average grain size of said inductor is equal to or larger than 4 μ

m.

5. The semiconductor device as set forth in claim 1, wherein said inductor contains copper having plain orientation [200].

6. The semiconductor device as set forth in claim 1, wherein the size of the grain contained in said inductor is larger as approaching a center from a side wall of said interconnect trench along a cross section perpendicular to the elongating orientation of said inductor, said interconnect trench having said inductor buried therein.

7. The semiconductor device as set forth in claim 1, wherein, in a cross section perpendicular to the elongating orientation of said inductor, grains of copper having plain orientation [111] are disposed in a side of the side wall of said interconnect trench of said inductor, and grains of copper having plain orientation [200] are disposed in the central portion of said interconnect trench.

8. The semiconductor device as set forth in claim 1, wherein, the average grain size of said inductor is equal to or higher than 10 times the average grain size of the interconnect of said second copper interconnect layer containing no inductor.