CAPACITOR OF SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

• US 20090115023A1
• Filed: 07/29/2008
• Published: 05/07/2009
• Est. Priority Date: 11/06/2007
• Status: Abandoned Application

• Current Assignee: Dongbu HiTek Co., Ltd.
• Original Assignee: Dongbu HiTek Co., Ltd.
• Inventors: Kim, Do Hun
• Application Number:
  US12/181,799
• Publication Number:
  US 20090115023A1
• Time in Patent Office: Days
• US Class Current: 257/532
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A capacitor of a semiconductor device and a method for manufacturing the same. In one example embodiment, a capacitor of a semiconductor device includes a first electrode, first dielectric layer, second electrode, second dielectric layer, and third electrode sequentially formed on a semiconductor substrate. The capacitor also includes a first contact coupled to the first electrode and to the third electrode. The capacitor further includes a second contact coupled to the second electrode.

Claims

1. A capacitor of a semiconductor device, comprising:

a first electrode, first dielectric layer, second electrode, second dielectric layer, and third electrode sequentially formed on a semiconductor substrate;

a first contact coupled to the first electrode and to the third electrode; and

a second contact coupled to the second electrode.

2. The capacitor of claim 1, wherein the first dielectric layer and the second electrode are extended beyond a top surface of the first electrode.

3. The capacitor of claim 1, wherein the first contact is formed to have a damascene structure.

4. The capacitor of claim 1, wherein the second contact is formed to have a damascene structure coupled to the second electrode.

5. A method for manufacturing a semiconductor device, comprising:

forming a first electrode by laminating a first conductive layer on a semiconductor substrate and etching the first conductive layer;

sequentially laminating a first dielectric layer, second conductive layer, second dielectric layer, and third conductive layer on an entire surface on which the first electrode is formed;

forming a third electrode by etching the third conductive layer and the second dielectric layer;

forming a second electrode by etching the second conductive layer and the first dielectric layer;

forming first and second contact holes reaching the first and second electrodes, respectively;

forming a first trench reaching the third electrode on top of the first contact hole;

forming a second trench on top of the second contact hole;

forming a first contact by filling in the first contact hole and the first trench with a conductive metal; and

forming a second contact by filling in the second contact hole and the second trench with a conductive metal.

6. The method of claim 5, wherein the second electrode, the first dielectric layer and the second electrode extend beyond a top surface of the first electrode.

7. The method of claim 5, wherein the first contact has a damascene structure.

8. The method of claim 7, wherein forming the first contact comprises filling in the first contact hole and the first trench with a conductive metal by Chemical Vapor Deposition (CVD).

9. The method of claim 5, wherein the second contact has a damascene structure.

10. The method of claim 9, wherein forming the second contact comprises filling in the second contact hole and the second trench with a conductive metal by Chemical Vapor Deposition (CVD).