SEMICONDUCTOR DEVICE HAVING THREE-DIMENSIONAL STACKED STRUCTURE AND METHOD OF FABRICATING THE SAME

• US 20090115042A1
• Filed: 06/03/2005
• Published: 05/07/2009
• Est. Priority Date: 06/04/2004
• Status: Abandoned Application

• Current Assignee: Rambus Inc.
• Original Assignee: Zycube Co., Ltd.
• Inventors: Koyanagi, Mitsumasa
• Application Number:
  US11/570,009
• Publication Number:
  US 20090115042A1
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2224/10135 Alignment aids
• CPC Class Codes: H01L 2224/10165 Alignment aids
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/1308 being stacked
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/13083 Three-layer arrangements
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13109 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/13609 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/13644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/14131 : being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/14505 : Bump connectors having different materials
• CPC Class Codes: H01L 2224/14515 : Bump connectors having different functions
• CPC Class Codes: H01L 2224/1703 : Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/17505 : Bump connectors having different materials
• CPC Class Codes: H01L 2224/17515 : Bump connectors having different functions
• CPC Class Codes: H01L 2224/29111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/2919 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/33181 : On opposite sides of the body
• CPC Class Codes: H01L 2224/45111 : Tin (Sn) as principal constituent
• CPC Class Codes: H01L 2224/73104 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73259 : Bump and HDI connectors
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/81097 : Heating
• CPC Class Codes: H01L 2224/8114 : Guiding structures outside the body
• CPC Class Codes: H01L 2224/81191 : wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81193 : wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81194 : Lateral distribution of the bump connectors
• CPC Class Codes: H01L 2224/81201 : Compression bonding
• CPC Class Codes: H01L 2224/8121 : using a reflow oven
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2224/81895 : between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2224/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/83007 : involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the layer connector during or after the bonding process
• CPC Class Codes: H01L 2224/83101 : as prepeg comprising a layer connector, e.g. provided in an insulating plate member
• CPC Class Codes: H01L 2224/83193 : wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83825 : Solid-liquid interdiffusion
• CPC Class Codes: H01L 2224/83862 : Heat curing
• CPC Class Codes: H01L 2224/83874 : Ultraviolet [UV] curing
• CPC Class Codes: H01L 2224/92125 : the second connecting process involving a layer connector
• CPC Class Codes: H01L 2224/92133 : the second connecting process involving a bump connector
• CPC Class Codes: H01L 2224/92135 : the second connecting process involving a layer connector
• CPC Class Codes: H01L 2224/92224 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/92244 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06582 : Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 23/295 : containing a filler H01L23/296 takes precedence
• CPC Class Codes: H01L 23/3135 : Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/95 : at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/12043 : Photo diode
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A three-dimensional stacked structured semiconductor device comprising semiconductor circuit layers stacked on a support substrate, and a method of fabricating the device are provided.

After fixing semiconductor chips 37 to a support substrate 31 with bump electrodes, gaps between the chips 37 are filled with an electrically insulative adhesive 38. Then, by polishing the reverses of the chips 37, the chips 37 are thinned to expose buried interconnections in the chips 37, thereby forming a first semiconductor circuit layer L1. Next, after fixing semiconductor chips 43 to the first semiconductor circuit layer L1 with bump electrodes 41 and 42 by way of an insulating layer 39, gaps between the chips 43 are filled with an electrically insulative adhesive 44. Then, by polishing the reverses of the chips 43, the chips 43 are thinned to expose buried interconnections in the chips 43, thereby forming a second semiconductor circuit layer L2. In a similar way, semiconductor chips 49 are fixed to the second semiconductor circuit layer L2 by way of an insulating layer 45, thereby forming a third semiconductor circuit layer L3. Dicing is performed as necessary. Thus, three-layer stacked structured semiconductor devices 30A, 30B, and 30C are obtained.

Claims

1. A semiconductor device having a three-dimensional stacked structure, comprising:

a support substrate; and

a stacked structure comprising first to n-th circuit layers (n is an integer equal to 2 or greater) stacked in sequence from a bottom of the structure to a top thereof in a predetermined stacking direction and unified with an electrically insulative adhesive, the structure being fixed to the substrate at the bottom;

wherein adjoining ones of the circuit layers in the stacked structure are mechanically and electrically interconnected with each other by way of connecting portions formed between the adjoining circuit layers, and are electrically insulated from each other by the adhesive in a region other than the connecting portions;

each of the first to n-th circuit layers is formed to include at least one semiconductor circuit; and

at least one of the first to n-th circuit layers is such that a physical size of the semiconductor circuit included in the said circuit layer in a plane perpendicular to the stacking direction is smaller than a physical size of the said circuit layer in the plane, and a side face of the said semiconductor circuit is covered with the adhesive.

2. The device according to claim 1, wherein a plurality of electrodes for external circuit connection are provided, the electrodes being located at the top of the stacked structure and electrically connected to at least one of the first to n-th circuit layers.

3. The device according to claim 1, wherein in each of the connecting portions for mechanical and electrical interconnection between the adjoining ones of the circuit layers in the stacked structure, a conductive contact formed to protrude on the semiconductor circuit of one of the two adjoining circuit layers and a conductive contact formed to protrude on the semiconductor circuit of the other of the two adjoining circuit layers are mechanically connected;

and

a gap between the adjoining ones of the circuit layers in the stacked structure is filled with the adhesive.

4. The device according to claim 1, wherein in each of the connecting portions for mechanical and electrical interconnection between the adjoining ones of the circuit layers in the stacked structure, a conductive contact is formed between the said circuit layers, and both ends of the conductive contact are mechanically connected to the adjoining circuit layers, respectively;

and

a gap between the adjoining ones of the circuit layers in the stacked structure is filled with the adhesive.

5. The device according to claim 1, wherein at least one of the first to n-th circuit layers comprises a rigid member extending between a face of the said circuit layer and an opposing face of an adjoining one of the circuit layers or the substrate.

6. The device according to claim 1, wherein at least one of the first to n-th circuit layers comprises a buried interconnection penetrating through the said circuit layer in the stacking direction;

and

electrical connection in the said circuit layer or to an adjoining one of the circuit layers is performed by using the buried interconnection.

7. The device according to claim 1, wherein a whole sidewall of the stacked structure is covered with the adhesive.

8. The device according to claim 1, wherein the circuit layer included in at least one of the first to n-th circuit layers is exposed from the adhesive covering a sidewall of the stacked structure.

9. The device according to claim 1, wherein at least one of the first to n-th circuit layers comprises semiconductor circuits arranged at predetermined positions in a plane perpendicular to the stacking direction.

10. The device according to claim 9, wherein the semiconductor circuits in the said circuit layer are electrically interconnected by way of a wiring layer.

11. The device according to claim 10, wherein the wiring layer is located between the said circuit layer and the other circuit layer adjoining thereto.

12. The device according to claim 1, wherein the semiconductor circuit included in at least one of the first to n-th circuit layers comprises at least one dummy semiconductor circuit.

13. The device according to claim 1, wherein the substrate comprises an inner circuit or a wiring line, the inner circuit or the wiring line being electrically connected to at least one of the first to n-th circuit layers.

14. The device according to claim 1, wherein the adhesive comprises a filler.

15. The device according to claim 1, wherein the semiconductor circuit included in at least one of the first to n-th circuit layers comprises a redundant structure.

16. A method of fabricating a semiconductor device having a three-dimensional stacked structure, said device comprising,

a support substrate;

and

a stacked structure comprising first to n-th circuit layers (n is an integer equal to 2 or greater) stacked in sequence from a bottom of the structure to a top thereof in a predetermined stacking direction and unified with an electrically insulative adhesive, the structure being fixed to the substrate at the bottom;

wherein at least one of the first to n-th circuit layers is such that a physical size of the semiconductor circuit included in the said circuit layer in a plane perpendicular to the stacking direction is smaller than a physical size of the said circuit layer in the said plane, and a side face of the said semiconductor circuit is covered with the adhesive;

said method comprising the steps of;

mechanically connecting at least one first semiconductor circuit to a surface of the support substrate at a predetermined position by way of first connecting portions;

filling a gap formed between the first semiconductor circuit and the substrate with a first electrically insulative adhesive, and curing the first adhesive;

polishing an opposite surface of the first semiconductor circuit to the substrate, where the gap is filled with the cured first adhesive, to adjust a thickness of the first semiconductor circuit to a predetermined value, thereby forming a first circuit layer constituting the stacked structure;

mechanically and electrically connecting at least one second semiconductor circuit to a surface of the first circuit layer at a predetermined position by way of second connecting portions;

filling a gap formed between the second semiconductor circuit and the first circuit layer with a second electrically insulative adhesive, and curing the second adhesive; and

polishing an opposite surface of the second semiconductor circuit to the substrate, where the gap is filled with the cured second adhesive, to adjust a thickness of the second semiconductor circuit to a predetermined value, thereby forming a second circuit layer constituting the stacked structure.

17. The method according to claim 16, wherein by repeating the three steps for forming the second circuit layer (n−

2) times, the first circuit layer comprising the at least one first semiconductor circuit, the second circuit layer comprising the at least one second semiconductor circuit, . . . , and an n-th circuit layer comprising at least one n-th semiconductor circuit are stacked on the substrate in this order, thereby forming the stacked structure.

18. The method according to claim 16, further comprising a step of forming a plurality of electrodes for external circuit connection at predetermined positions on the n-th circuit layer;

wherein the electrodes for external circuit connection are electrically connected to at least one of the first to n-th circuit layers.

19. The method according to claim 16, wherein each of the second connecting portions used in the step of mechanically and electrically connecting the at least one second semiconductor circuit to the surface of the first circuit layer at the predetermined position comprises a conductive contact formed to protrude on the second semiconductor circuit and a conductive contact formed to protrude on the first circuit layer;

and

the first circuit layer and the at least one second semiconductor circuit are mechanically and electrically connected by mechanically connecting the contacts to each other directly or by way of a bonding metal.

20. The method according to claim 16, wherein each of the second connecting portions used in the step of mechanically and electrically connecting the at least one second semiconductor circuit to the surface of the first circuit layer at the predetermined position comprises a conductive contact formed to protrude on the second semiconductor circuit or the first circuit layer;

wherein the first circuit layer and the at least one second semiconductor circuit are mechanically and electrically connected by mechanically connecting each end of the contact to the first circuit layer and the at least one second semiconductor circuit, respectively.

21. The method according to claim 16, wherein at least one of the first semiconductor circuit and the second semiconductor circuit comprises a rigid member protruding toward an opposing face of the substrate or the first circuit layer adjoining thereto;

and

the rigid member is used as a stopper for positioning the first semiconductor circuit and/or the second semiconductor circuit in the stacking direction.

22. The method according to claim 16 wherein at least one of the first semiconductor circuit and the second semiconductor circuit comprises a buried interconnection that does not penetrate through the said semiconductor circuit;

and

when the opposite surface of the said semiconductor circuit to the substrate is polished, the interconnection is turned to a penetrating state where the interconnection penetrates through the said semiconductor circuit.

23. The method according to claim 16, wherein the first circuit layer includes a plurality of the first semiconductor circuits and the second circuit layer includes a plurality of the second semiconductor circuits.

24. The method according to claim 16, wherein the first circuit layer has a physical size in a plane perpendicular to the stacking direction larger than a physical size of the at least one first semiconductor circuit in the plane;

a side face of the first semiconductor circuit is covered with the first adhesive;

the second circuit layer has a physical size in a plane perpendicular to the stacking direction larger than a physical size of the at least one second semiconductor circuit in the plane; and

a side face of the second semiconductor circuit is covered with the second adhesive.

25. The method according to claim 16, wherein filling the gap with the first or second adhesive is performed by spraying the first or second adhesive.

26. The method according to claim 16, wherein filling the gap with the first or second adhesive is performed by immersing in a liquid adhesive the first semiconductor circuit fixed to the substrate or the second semiconductor circuit fixed to the first semiconductor circuit.

27. The method according to claim 16, wherein filling the gap with the first or second adhesive is performed by immersing in said liquid adhesive the substrate and the first semiconductor circuit sandwiched by a pair of pressing members or the first and second semiconductor circuits sandwiched by a pair of pressing members.

28. The method according to claim 16, wherein filling the gap with the first or second adhesive is performed by placing the substrate and the first semiconductor circuit or the first and second semiconductor circuits in a member having a closed space, and injecting the liquid adhesive into the space under pressure.

29. The method according to claim 16, wherein the first semiconductor circuits or the second semiconductor circuits are regularly placed on the substrate or the first circuit layer and thereafter, gaps between the first semiconductor circuits or the second semiconductor circuits and their peripheries are coated with at least one of the first and second adhesives using a dispenser.

30. The method according to claim 16. wherein when the first adhesive filled in the gaps are cured, a layer for preventing a warp of the substrate is placed on an opposite surface of the substrate to the first circuit layer.

31. The method according to claim 16, wherein when the gaps are filled with the first adhesive and the first adhesive is cured, a warp preventing layer for preventing a warp of the substrate is placed on an opposite surface of the substrate to the first circuit layer.

32. The method according to claim 16 wherein when the gaps are filled with the first adhesive or the first adhesive is cured, a first warp preventing layer for preventing a warp of the substrate is placed on an opposite surface of the substrate to the first circuit layer;

and

when the gaps are filled with the second adhesive or the second adhesive is cured, a second warp preventing layer for preventing a warp of the substrate is placed on the first warp preventing layer.

33. The method according to claim 16, further comprising a step of warping the substrate toward an opposite side to a warp of the substrate to be generated by curing of the first adhesive, which is performed after mechanically connecting the first semiconductor circuit to the substrate by way of the first connecting portions.

34. The method according to claim 16 wherein at least one of the first and second adhesives contains a filler.

35. The method according to claim 16 further comprising a step of dicing the substrate and the stacked structure along a cutting plane or planes parallel to the stacking direction to thereby form semiconductor devices.

36. The method according to claim 16 wherein the semiconductor circuit included in at least one of the first to n-th circuit layers comprises a redundant structure.