Robust multi-layer wiring elements and assemblies with embedded microelectronic elements

• US 20090115047A1
• Filed: 10/08/2008
• Published: 05/07/2009
• Est. Priority Date: 10/10/2007
• Status: Abandoned Application

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Haba, Belgacem, Oganesian, Vage, Endo, Kimitaka
• Application Number:
  US12/287,380
• Publication Number:
  US 20090115047A1
• Time in Patent Office: Days
• US Class Current: 257/690
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/1023 the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H05K 1/185 : Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit semiconductor chips encapsulated by interconnect and support structures H01L23/5389, H01L24/00
• CPC Class Codes: H05K 2201/0355 : Metal foils
• CPC Class Codes: H05K 2201/0361 : Etched tri-metal structure, i.e. metal layers or metal patterns on both sides of a different central metal layer which is later at least partly etched
• CPC Class Codes: H05K 2201/0382 : Continuously deformed conductors
• CPC Class Codes: H05K 2201/096 : Vertically aligned vias, holes or stacked vias
• CPC Class Codes: H05K 2203/0384 : Etch stop layer, i.e. a buried barrier layer for preventing etching of layers under the etch stop layer
• CPC Class Codes: H05K 2203/0733 : Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
• CPC Class Codes: H05K 2203/1189 : Pressing leads, bumps or a die through an insulating layer
• CPC Class Codes: H05K 3/0038 : combined with laser drilling through a metal layer
• CPC Class Codes: H05K 3/4038 : Through-connections; Vertical interconnect access [VIA] connections H05K3/403, H05K3/42 take precedence
• CPC Class Codes: H05K 3/4647 : by applying an insulating layer around previously made via studs
• CPC Class Codes: H05K 3/4652 : Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern H05K3/4647 takes precedence

Abstract

An interconnect element 130 can include a dielectric layer 116 having a top face 116b and a bottom face 116a remote from the top face, a first metal layer defining a plane extending along the bottom face and a second metal layer extending along the top face. One of the first or second metal layers, or both, can include a plurality of conductive traces 132, 134. A plurality of conductive protrusions 112 can extend upwardly from the plane defined by the first metal layer 102 through the dielectric layer 116. The conductive protrusions 112 can have top surfaces 126 at a first height 115 above the first metal layer 132 which may be more than 50% of a height of the dielectric layer. A plurality of conductive vias 128 can extend from the top surfaces 126 of the protrusions 112 to connect the protrusions 112 with the second metal layer.

Claims

1. An interconnect element, comprising:

a dielectric layer having a top face and a bottom face remote from the top face;

a first metal layer defining a plane extending along the bottom face;

a second metal layer extending along the top face, at least one of the first and second metal layers including a plurality of conductive traces;

a plurality of conductive protrusions extending upwardly from the plane defined by the first metal layer through the dielectric layer, the conductive protrusions having top surfaces at a first height above the first metal layer, the first height being greater than 50% of a height of the dielectric layer above the first metal layer; and

a plurality of conductive vias extending from the top surfaces through openings in the dielectric layer to conductively connect the conductive protrusions with the second metal layer, wherein at least one of the conductive vias has a first width in contact with the top surface of the conductive protrusion, the first width being less than a width of the top surface.

2. An interconnect element as set forth in claim 1, wherein the at least one conductive protrusion has a wall extending downwardly away from the top surface, at least one conductive via contacting the conductive protrusion only at the top surface.

3. An interconnect element, comprising:

a dielectric layer having a top face and a bottom face remote from the top face;

a first metal layer defining a plane extending along the bottom face;

a second metal layer extending along the top face, at least one of the first and second metal layers including a plurality of conductive traces;

a plurality of conductive protrusions extending upwardly from the plane defined by the first metal layer through the dielectric layer; and

a plurality of plated features extending through openings in the dielectric layer to conductively connect the conductive protrusions with the second metal layer.

4. An interconnect element as set forth in claim 3, wherein each of the first and second metal layers includes a plurality of conductive traces.

5. An interconnect element as set forth in claim 3, wherein the conductive protrusions include etched metal posts.

6. An interconnect element as set forth in claim 3, wherein the conductive protrusions include a plated metal layer.

7. An interconnect element as set forth in claim 6, wherein the conductive protrusions include hollow conductive protrusions.

8. An interconnect element as set forth in claim 3, wherein the first metal layer includes planar portions aligned with the plane and the protruding portions extending away from the plane, the protruding portions defining the conductive protrusions.

9. An interconnect element as set forth in claim 3, wherein the conductive protrusions have frusto-conical shape.

10. An interconnect element as set forth in claim 3, wherein the second metal layer includes a plurality of conductive traces, the interconnect element further comprising a second dielectric layer overlying the second metal layer, a third metal layer overlying the second dielectric element, a plurality of second conductive protrusions extending upwardly from the second metal layer through the second dielectric layer, and a plurality of second plated features extending through openings in the second dielectric layer to conductively connect the second conductive protrusions with the third metal layer.

11. An interconnect element as set forth in claim 8, wherein the third metal layer includes a plurality of conductive traces.

12. An interconnect element as set forth in claim 8, further comprising a plurality of third conductive protrusions extending upwardly from the third metal layer.

13. A packaged microelectronic element, comprising:

a dielectric layer having a top face and a bottom face remote from the top face;

a first metal layer defining a plane extending along the bottom face;

a second metal layer extending along the top face, at least one of the first and second metal layers including a plurality of conductive traces;

a plurality of conductive protrusions extending upwardly from the plane defined by the first metal layer through the dielectric layer;

a microelectronic element disposed between the first and second wiring layers, the microelectronic element having a contact-bearing face separated from the second metal layer by the dielectric layer; and

a plurality of plated features extending through openings in the dielectric layer to conductively connect the conductive protrusions and contacts of the microelectronic element with the second metal layer.

14. A packaged microelectronic element as set forth in claim 13, wherein each of the first and second metal layers includes a plurality of conductive traces.

15. A packaged microelectronic element as set forth in claim 13, wherein the conductive protrusions include etched metal posts.

16. A packaged microelectronic element as set forth in claim 13, wherein the conductive protrusions include a plated metal layer.

17. A packaged microelectronic element as set forth in claim 14, wherein the conductive protrusions include hollow conductive protrusions.

18. A packaged microelectronic element as set forth in claim 13, wherein the first metal layer includes planar portions aligned with the plane and protruding portions extending away from the plane, the protruding portions defining the conductive protrusions.

19. A packaged microelectronic element as set forth in claim 13, wherein the conductive protrusions have frusto-conical shape.

20. A multiple wiring layer interconnect element having at least one of an active or passive component incorporated therein, comprising:

a dielectric layer having a top face and a bottom face remote from the top face;

a first metal layer defining a plane extending along the bottom face;

a second metal layer extending along the top face,

at least one of the first and second metal layers including a plurality of conductive traces;

a plurality of conductive protrusions extending from the plane upwardly through the dielectric layer;

at least one of an active or passive component disposed between the first and second metal layers, the component having a plurality of terminals confronting the second metal layer and separated from the second metal layer by the dielectric layer; and

a plurality of plated features extending through openings in the dielectric layer to conductively connect the conductive protrusions and the terminals of the component with the second metal layer.

21. A method of fabricating an interconnect element having a plurality of wiring layers separated from each other by at least one dielectric layer, comprising:

(a) laminating a dielectric layer and a first metal layer atop the dielectric layer onto a base element including a second metal layer having at least portions defining a plane and a plurality of conductive protrusions extending upwardly from the plane, such that portions of the dielectric layer separate adjacent ones of the conductive protrusions;

(b) forming openings in the dielectric layer which expose at least top surfaces of the conductive protrusions; and

(c) plating a metal onto the exposed surfaces of the conductive protrusions within the openings to form plated features connecting the conductive protrusions with the first metal layer.

22. A method as set forth in claim 21, further comprising patterning the second metal layer to form wiring patterns after forming the plated features.

23. A method as set forth in claim 21, further comprising patterning the first metal layer to form wiring patterns after forming the plated features.

24. A method as set forth in claim 21, wherein the dielectric layer includes an uncured dielectric element and step (a) is formed by pressing the uncured dielectric element onto the first metal layer and the conductive protrusions thereon at a temperature of about 200°

C. or less and then curing the uncured dielectric element.

25. A method as set forth in claim 21, wherein during step (a), the first and second metal layers define continuous planes.

26. A method as set forth in claim 21, wherein during step (a), at least one of the first and second metal layers includes a plurality of individual traces extending in directions defining a plane.

27. A method as set forth in claim 21, wherein during step (a) the first metal layer includes a plurality of openings and step (a) includes laminating the first metal layer onto the base element such that the plurality of openings therein are aligned with the conductive protrusions.

28. A method as set forth in claim 21, wherein the openings in the dielectric layer are formed by etching.

29. A method as set forth in claim 21, wherein the openings in the dielectric layer are formed by laser ablation.

30. A method as set forth in claim 21, wherein when the first metal layer is laminated with the dielectric layer to the base element in step (a), the first metal layer has openings aligned with the conductive protrusions of the base element and the first metal layer is joined with a third metal layer overlying the first metal layer.

31. A method as set forth in claim 30, further comprising, patterning the third metal layer to form second conductive protrusions extending upwardly from the first metal layer.

32. A method as set forth in claim 30, further comprising etching the third metal layer attached to the first metal layer to form the conductive protrusions of the base element.

33. A method as set forth in claim 30, further comprising plating the third metal layer into recesses in a mandrel and removing the mandrel to form the conductive protrusions.

34. A method as set forth in claim 21, wherein the conductive protrusions include hollow conductive protrusions.

35. A method as set forth in claim 31, further comprising:

(d) laminating a second dielectric layer and a fourth metal layer atop the dielectric layer onto the first metal layer and the plurality of second conductive protrusions extending upwardly therefrom such that portions of the second dielectric layer separate adjacent ones of the second conductive protrusions;

(e) forming openings in the second dielectric layer which expose at least top surfaces of the second conductive protrusions; and

(f) plating a metal onto the exposed surfaces of the second conductive protrusions within the openings in the second dielectric layer to form second plated features connecting the second conductive protrusions with the fourth metal layer.

36. A method as set forth in claim 35, wherein during step (d) the first, second and fourth metal layers define continuous planes.

37. A method as set forth in claim 35, wherein during step (d), at least one of the first and fourth metal layers includes a plurality of individual traces extending in directions defining a plane.

38. A method as set forth in claim 35, wherein when the fourth metal layer is laminated with the second dielectric layer onto the first metal layer and second conductive protrusions extending therefrom in step (d), the fourth metal layer has openings aligned with the second conductive protrusions and the fourth metal layer is attached to a fifth metal layer overlying the fourth metal layer.

39. A method as set forth in claim 38, further comprising, prior to step (e), patterning the fifth metal layer to form third conductive protrusions extending upwardly from the fourth metal layer.

40. A method of packaging a microelectronic element between wiring layers of an interconnect element having a plurality of wiring layers separated from each other by at least one dielectric layer, comprising:

laminating a dielectric layer and a first metal layer atop the dielectric layer onto a first element including second metal layer having at least portions defining a plane, a plurality of conductive protrusions extending upwardly from the plane and a microelectronic element having a first face adjacent to the plane, the step of laminating performed such that portions of the dielectric layer separate adjacent ones of the conductive protrusions and separate the microelectronic element from the conductive protrusions;

forming openings in the dielectric layer which expose contacts at a second face of the microelectronic element and at least top surfaces of the conductive protrusions; and

plating a metal onto the exposed contacts and exposed surfaces of the conductive protrusions within the openings to form plated features connecting the contacts and the conductive protrusions with the first metal layer.

41. A method as set forth in claim 40, wherein the first metal layer includes a thermally conductive plate attached to the first face of the microelectronic element.

42. A method of forming an interconnect element including at least one of an active or passive component between respective wiring layers of the interconnect element having a plurality of wiring layers separated from each other by at least one dielectric layer, comprising:

laminating a dielectric layer and a first metal layer atop the dielectric layer onto a first element including second metal layer having at least portions defining a plane, a plurality of conductive protrusions extending upwardly from the plane and at least one of an active or passive component having a surface overlying the plane, the step of laminating performed such that portions of the dielectric layer separate adjacent ones of the conductive protrusions and the electric device from each other;

forming openings in the dielectric layer which expose contacts of the electric device and at least top surfaces of the conductive protrusions; and

plating a metal onto the exposed contacts and exposed surfaces of the conductive protrusions within the openings to form plated features connecting the contacts and the conductive protrusions with the second metal layer.