Interposer And Semiconductor Device

• US 20090115050A1
• Filed: 06/02/2006
• Published: 05/07/2009
• Est. Priority Date: 06/06/2005
• Status: Active Grant

• Current Assignee: Achlys Technologies Inc.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Haga, Motoharu, Kasuya, Yasumasa, Fujii, Sadamasa
• Granted Patent: US 8,022,532 B2
• Time in Patent Office: Days
• US Class Current: 257/701
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/3735 Laminates or multilayers, e.g. direct bond copper ceramic substrates
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/07802 not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H05K 2201/10378 Interposers
• CPC Class Codes: H05K 2201/10734 : Ball grid array [BGA]; Bump grid array
• CPC Class Codes: H05K 3/3436 : having an array of bottom contacts, e.g. pad grid array or ball grid array components

Abstract

An interposer and a semiconductor device including the interposer are provided, which can prevent thermal warpage of an insulative substrate thereof. The interposer is to be provided together with a semiconductor chip in a semiconductor device and, when the semiconductor device is mounted on a mount board, disposed between the semiconductor chip and the mount board. The interposer includes: an insulative substrate of an insulative resin; an island provided on one surface of the insulative substrate to be bonded to a rear surface of the semiconductor chip via a bonding agent; a thermal pad provided on the other surface of the insulative substrate opposite from the one surface in generally opposed relation to the island with the intervention of the insulative substrate; and a thermal via extending through the insulative substrate from the one surface to the other surface to connect the island to the thermal pad in a thermally conductive manner.

Claims

1. An interposer to be provided together with a semiconductor chip in a semiconductor device and, when the semiconductor device is mounted on a mount board, disposed between the semiconductor chip and the mount board, the interposer comprising:

an insulative substrate of an insulative resin;

an island provided on one surface of the insulative substrate to be bonded to a rear surface of the semiconductor chip via a bonding agent;

a thermal pad provided on the other surface of the insulative substrate opposite from the one surface in generally opposed relation to the island with the intervention of the insulative substrate; and

a thermal via extending through the insulative substrate from the one surface to the other surface to connect the island to the thermal pad in a thermally conductive manner.

2. The interposer according to claim 1, further comprising:

internal terminals provided on the one surface of the insulative substrate for electrical connection to the semiconductor chip;

external terminals provided on the other surface of the insulative substrate for electrical connection to lands on the mount board; and

inter-terminal connection vias extending through the insulative substrate from the one surface to the other surface to respectively electrically connect the internal terminals to the external terminals.

3. The interposer according to claim 2, further comprising a thermal bump provided on the thermal pad and adapted to abut against the mount board with the semiconductor device mounted on the mount board.

4. The interposer according to claim 3,

wherein the island, the thermal pad, the thermal via and the thermal bump are electrically conductive,

wherein the bonding agent is composed of a metal material,

wherein the thermal bump is adapted to abut against a ground terminal on the mount board with the semiconductor device mounted on the mount board.

5. The interposer according to claim 4, wherein the bonding agent is a high melting point solder.

6. The interposer according to claim 2, wherein the thermal vias are arranged at a higher density than the inter-terminal connection vias.

7. An interposer comprising:

an insulative substrate having via-holes arranged in a matrix array with an electrically conductive island provided on a front surface thereof;

wherein the insulative substrate has a heat dissipation via-hole provided in addition to the via-holes arranged in the matrix array in a region thereof opposed to the island.

8. The interposer according to claim 7, wherein metal terminals are provided on a rear surface of the insulative substrate and respectively electrically connected to the via-holes in the region of the insulative substrate opposed to the island.

9. The interposer according to claim 8, wherein the via-holes and/or the heat dissipation via-hole are filled with a metal filler.

10. A semiconductor device comprising:

a semiconductor chip;

an insulative substrate of an insulative resin;

an island provided on one surface of the insulative substrate and bonded to a rear surface of the semiconductor chip via a bonding agent;

a thermal pad provided on the other surface of the insulative substrate opposite from the one surface in generally opposed relation to the island with the intervention of the insulative substrate; and

a thermal via extending through the insulative substrate from the one surface to the other surface to connect the island to the thermal pad in a thermally conductive manner.

11. The semiconductor device according to claim 10, further comprising:

internal terminals provided on the one surface of the insulative substrate and electrically connected to the semiconductor chip;

external terminals provided on the other surface of the insulative substrate for electrical connection to lands on a mount board on which the semiconductor device is mounted; and

inter-terminal connection vias extending through the insulative substrate from the one surface to the other surface to respectively electrically connect the internal terminals to the external terminals.

12. The semiconductor device according to claim 11, further comprising a thermal bump provided on the thermal pad and adapted to abut against the mount board with the semiconductor device mounted on the mount board.

13. The semiconductor device according to claim 12,

wherein the island, the thermal pad, the thermal via and the thermal bump are electrically conductive,

wherein the bonding agent is composed of a metal material,

wherein the thermal bump is adapted to abut against a ground terminal on the mount board with the semiconductor device mounted on the mount board.

14. The semiconductor device according to claim 13, wherein the bonding agent is a high melting point solder.

15. The semiconductor device according to claim 11, wherein the thermal vias are arranged at a higher density than the inter-terminal connection vias.

16. A semiconductor device comprising:

an insulative substrate having via-holes arranged in a matrix array with an electrically conductive island provided on a front surface thereof; and

a semiconductor chip die-bonded to the island via an electrically conductive layer;

wherein the insulative substrate has a heat dissipation via-hole provided in addition to the via-holes arranged in the matrix array in a region thereof opposed to the island.

17. The semiconductor device according to claim 16, wherein metal terminals are provided on a rear surface of the insulative substrate and respectively electrically connected to the via-holes in the region of the insulative substrate opposed to the island.

18. The semiconductor device according to claim 17, wherein the via-holes and/or the heat dissipation via-hole are filled with a metal filler.