SPACER PROCESS FOR ON PITCH CONTACTS AND RELATED STRUCTURES

• US 20090115064A1
• Filed: 11/01/2007
• Published: 05/07/2009
• Est. Priority Date: 11/01/2007
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Kiehlbauch, Mark, Sandhu, Gurtej, Kramer, Steve, Smythe, John
• Granted Patent: US 7,737,039 B2
• Time in Patent Office: Days
• US Class Current: 257/773
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/0338 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 438/942 Masking

Abstract

Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. Also disclosed are structures associated with the methods. In one or more embodiments, contacts are formed on pitch with other structures, such as conductive interconnects. The interconnects may be formed by pitch multiplication. To form the contacts, in some embodiments, a pattern corresponding to some of the contacts is formed in a selectively definable material such as photoresist. The features in the selectively definable material are trimmed to desired dimensions. Spacer material is blanket deposited over the features in the selectively definable material and the deposited material is then etched to leave spacers on sides of the features. The selectively definable material is removed to leave a mask defined by the spacer material. The pattern defined by the spacer material may be transferred to a substrate, to form on pitch contacts. In some embodiments, the on pitch contacts may be used to electrically contact conductive interconnects in the substrate.

Claims

1. A method for semiconductor processing, comprising:

providing a row of laterally separated mandrels formed of a mandrel material, the row extending along a first axis;

providing first and second laterally spaced blocks of mandrel material on a same plane as the mandrels, the first and second blocks extending a length of the row, wherein the mandrels are disposed between the first and second blocks;

blanket depositing a layer of spacer material over the mandrels;

anisotropically etching the layer of spacer material to form spacers on sides of the mandrels;

selectively removing the mandrels relative to the spacer material, wherein remaining spacer material forms a mask pattern; and

transferring the mask pattern to the substrate to form a row of contact vias in the substrate.

2. The method of claim 1, wherein the mandrel material is photoresist, wherein providing the row of laterally separated mandrels and providing first and second laterally spaced blocks of mandrel material comprises photolithographically defining the row of laterally separated mandrels and the first and second laterally spaced blocks.

3. The method of claim 1, wherein transferring the mask pattern to the substrate comprises:

transferring the mask pattern to a primary masking layer; and

etching the substrate through the primary masking layer to etch the mask pattern into the substrate.

4. The method of claim 3, wherein transferring the mask pattern to the substrate comprises transferring the mask pattern to an anti-reflective coating before transferring the mask pattern to the primary masking layer.

5. The method of claim 3, wherein the primary masking layer comprises amorphous carbon.

6. The method of claim 3, further comprising performing a carbon strip after transferring the mask pattern to the primary masking layer and before etching the substrate.

7. The method of claim 3, further comprising selectively removing the primary masking layer after etching the substrate.

8. The method of claim 1, wherein the first and second blocks extend along a second axis substantially transverse to the first axis.

9. The method of claim 1, wherein the mandrels contact the first and second blocks.

10. The method of claim 9, wherein the mandrels are provided with a mid-section wider than ends of the mandrels in contact with the first and second blocks.

11. The method of claim 1, wherein the mandrels form a checkerboard pattern with sacrificial features in contact with the first and second blocks.

12. The method of claim 11, wherein mandrels and the sacrificial features are arranged in three substantially parallel rows, wherein a first row of sacrificial features contacts the first block, a second row of sacrificial features contacts the second block and the mandrels form the third row.

13. The method of claim 1, wherein the mandrels have an oval cross-sectional shape, as observed from a top down view.

14. The method of claim 1, wherein transferring the mask pattern to the substrate exposes conductive interconnects in the substrate.

15. A method for integrated circuit fabrication, comprising:

providing a row of pillars on a level above a substrate, the pillars having a linear density Z; and

replacing the row of pillars with a mask having a row of holes, the mask and holes disposed on the level, the holes having a width of about 60 nm or less, at least some of the holes disposed at a location formerly occupied by a pillar, the holes having a linear density at least about 1.5 times Z.

16. The method of claim 15, wherein the linear density of the holes is about 2 times Z.

17. The method of claim 15, wherein the pillars are formed of photoresist, wherein providing the row of pillars comprises:

photolithographically forming features in the photoresist; and

trimming the photoresist features to form the pillars.

18. The method of claim 15, wherein replacing the row of pillars with the mask having the row of holes comprises:

depositing spacer material on the pillars;

etching the spacer material to form spacers on sides of the pillars; and

selectively removing the pillars.

19. A partially fabricated integrated circuit, comprising:

a plurality of pillars extending on a first axis;

first and second laterally spaced blocks formed of the same material as the pillars, the first and second blocks extending at least between a first and a last of the pillars on the first axis, wherein the pillars are disposed between the first and second blocks; and

spacers disposed on sides of the pillars and on sides of the first and the second blocks.

20. The partially fabricated integrated circuit of claim 19, wherein only one row of pillars is disposed between the first and second blocks.

21. The partially fabricated integrated circuit of claim 19, wherein the pillars comprise photoresist.

22. The partially fabricated integrated circuit of claim 21, wherein the width is about 30 nm or less.

23. The partially fabricated integrated circuit of claim 21, wherein a distance between the spacers at the sides of the pillars is about 50 nm or less.

24. The partially fabricated integrated circuit of claim 19, further comprising a plurality of conductive interconnects below the spacers and the pillars, the pillars vertically aligned with at least some of the conductive interconnects.

25. The partially fabricated integrated circuit of claim 19, wherein the partially fabricated integrated circuit is a partially fabricated memory device.