Semiconductor integrated circuit and electronic device

• US 20090115442A1
• Filed: 12/08/2008
• Published: 05/07/2009
• Est. Priority Date: 12/27/1999
• Status: Active Grant

• Current Assignee: Longitude Semiconductor S.à r.l. (Vector Capital Corporation)
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Nishio, Yoji, Funaba, Seiji
• Granted Patent: US 7,725,778 B2
• Time in Patent Office: Days
• US Class Current: 324/754.60
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/025 in signal lines
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: H05K 1/0248 Skew reduction or using delay lines
• CPC Class Codes: H05K 1/0268 for electrical inspection or testing
• CPC Class Codes: H05K 1/14 Structural association of two or more printed circuits providing electric connection to or between printed circuits H05K1/11, H01R12/00
• CPC Class Codes: H05K 2201/044 Details of backplane or midplane for mounting orthogonal PCBs
• CPC Class Codes: H05K 2201/09781 Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components

Abstract

A dummy wiring 25 is provided for simulating an actual wiring 26 connecting semiconductor integrated circuits 2 and 6 on a circuit board. The semiconductor integrated circuit comprises a data output circuit 28 capable of variably setting the slew rate and a circuit 29 for measuring signal delay time between a signal sending point and a signal reflection point (characteristic impedance mismatching point) using the dummy wiring 25, and the delay time so obtained by the measuring circuit is used for the determination of the signal transition time of the output circuit. The transition time of the signal is set at least twice of the signal delay time between the signal sending point and the wiring branch at the nearest end. In this way, signal transmission with alleviated reflection by the reflection point at the nearest end is realized.

Claims

1. An electronic device including a motherboard mounted with a memory controller and a memory module interfaced to said memory controller, mounted with a plurality of memories and, comprising:

a first dummy wiring which simulates and feeds back a path from said memory to a given characteristic impedance mismatching point present along a signal wiring reaching to said memory controller; and

a second dummy wiring which simulates and feeds back a path from said memory controller to a given characteristic impedance mismatching point present along a signal wiring reaching to said memory;

wherein said memory includes;

a first output circuit capable of variably setting signal transition time;

a first signal generating circuit which generates a test signal for the use in a setting operation of said signal transition time; and

a first controlling circuit which sets said signal transition time to said first output circuit based on a transmission delay time of said test signal which has been outputted from said first signal generating circuit to said first dummy wiring and fed back; and

said memory controller includes;

a second output circuit capable of variably setting signal transition time;

a second signal generating circuit which generates a test signal for setting said signal transition time; and

a second controlling circuit which sets said signal transition time to said second output circuit based on a transmission delay time of said test signal which has been outputted from said second signal generating circuit to said second dummy wiring and fed back.

2. An electronic device according to claim 1 wherein said first output circuit outputs data strobe signals for the data read out from said memory, and said second output circuit outputs data strobe signals for the output of write data.

3. An electronic device including a motherboard mounted with a memory controller and a memory module mounted with a plurality of memories interfaced with said memory controller through a connector comprising:

a first dummy wiring which simulates and feeds back a signal wiring path from said memory controller to said memory; and

a second dummy wiring which simulates and feeds back a signal wiring path from said memory controller to said connector along a signal wiring path from said memory to said memory controller;

wherein said memory includes;

a first output circuit capable of variably setting signal transition time; and

said memory controller includes;

a second output circuit capable of variably setting signal transition time;

a signal generating circuit which generates a test signal for the use in a setting operation of said signal transition time; and

a second controller which sets said signal transition time to said second output circuit based on a transmission delay time of the test signal which has been outputted from said signal generating circuit to said first dummy wiring and fed back; and

a first controller which determines said signal transition time of said first output circuit based on a difference in transmission time between said test signal which has been outputted from said signal generating circuit to said first dummy wiring and fed back and the test signal which has been outputted from said signal generating circuit to said second dummy wiring and fed back.

4. An electronic circuit including a circuit board mounted with a first semiconductor integrated circuit and a second semiconductor integrated circuit, said first semiconductor integrated circuit comprising:

an output circuit capable of variably setting a slew rate;

a test output controlling circuit which controls said output circuit to output a test signal for the use in a setting operation of said slew rate to a first signal line; and

a slew rate controlling circuit which controls said slew late of said output circuit to be alleviated according to the state of a signal returned from the outside of the circuit via a second signal line in response to said test signal outputted from said output circuit;

said second semiconductor integrated circuit comprising;

a determination circuit which determines the presence or absence of fluctuation in the waveform of said test signal supplied to said first signal line and having said second signal line output a signal corresponding to the determination result.