Method, device and apparatus for accessing a non-volatile memory array

• US 20090116288A1
• Filed: 11/07/2008
• Published: 05/07/2009
• Est. Priority Date: 11/07/2007
• Status: Active Grant

• Current Assignee: Spansion Israel Limited (Infineon Technologies AG)
• Original Assignee: Spansion Israel Limited (Infineon Technologies AG)
• Inventors: Varkony, Roni
• Granted Patent: US 8,120,960 B2
• Time in Patent Office: Days
• US Class Current: 365/185.130
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out

Abstract

A non-volatile memory (NVM) having an array of memory cells and a unidirectional multiplexer (UMUX), the UMUX may be comprised of two or more address line ports adapted to receive addressing signals corresponding with elements in the memory array, and a set of switching transistors adapted to switch a supply voltage in accordance with the addressing signal such that current only flows into the array.

Claims