METHOD OF MAKING INTEGRATED CIRCUIT EMBEDDED WITH NON-VOLATILE ONE-TIME - PROGRAMMABLE AND MULTIPLE-TIME PROGRAMMABLE MEMORY

• US 20090116291A1
• Filed: 11/03/2008
• Published: 05/07/2009
• Est. Priority Date: 11/01/2007
• Status: Active Grant

• Current Assignee: Invensas Corporation
• Original Assignee: Jonker LLC
• Inventors: Liu, David K.Y.
• Granted Patent: US 7,787,304 B2
• Time in Patent Office: Days
• US Class Current: 365/185.180
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 2216/10 Floating gate memory cells with a single polysilicon layer
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/60 the control gate being a doped region, e.g. single-poly memory cell

Abstract

A programmable non-volatile device is made which uses a floating gate that functions as a FET gate that overlaps a portion of a source/drain region. This allows a programming voltage for the device to be imparted to the floating gate through capacitive coupling, thus changing the state of the device. The invention can be used in environments such as data encryption, reference trimming, manufacturing ID, security ID, and many other applications.

Claims

1. A method of forming a non-volatile programmable memory device situated on:

a substrate comprising;

forming a gate for non-volatile programmable memory device from a first layer;

wherein said first layer is shared by the non-volatile programmable memory device and at least one other device also situated on the substrate and associated with a logic gate and/or a volatile memory;

forming a drain region; and

capacitively coupling said gate with said drain region by overlapping a portion of said gate with said drain region.

2. The method of claim 1 wherein said first layer is polysilicon.

3. The method of claim 1 wherein said first layer is an insulating layer.

4. The method of claim 3 wherein said gate further includes impurities, which impurities are introduced during a source or drain implant step.

5. The method of claim 1 wherein said device is formed with n-type channel.

6. The method of claim 1 wherein said non-volatile programmable memory device is embedded in a computing circuit and formed entirely by masks used to form other logic and/or memory n-channel devices in said processing circuit.

7. The method of claim 6 wherein said non-volatile programmable memory device is embedded in a computing circuit and formed entirely by CMOS processing steps used to form other logic and/or memory devices in said computing circuit.

8. The method of claim 1 wherein said non-volatile programmable memory device is associated with one of the following:

a data encryption circuit;

a reference trimming circuit;

a manufacturing ID; and

/or a security ID.

9. The method of claim 1, wherein said capacitive coupling takes place in a first trench situated in the substrate.

10. The method of claim 9 wherein a set of second trenches in said substrate are used as embedded DRAM.

11. The method of claim 1 further including a step:

forming a second programmable device coupled in a paired latch arrangement such a datum and its compliment can be stored in said paired latch.

12. The method of claim 1 wherein said non-volatile programmable memory device can only be programmed once.

13. The method of claim 1 wherein said non-volatile programmable memory device can be erased and re-programmed.

14. The method of claim 1 wherein said non-volatile programmable memory device is used to store an identification code for a wafer.

15. The method of claim 1 further including a step:

programming said non-volatile programmable memory device during manufacture of a wafer to store an identification code.

16. The method of claim 14 further including a step:

programming a second non-volatile programmable memory device during manufacture of the wafer to store a second identification code.

17. The method of claim 11 wherein said non-volatile programmable memory device has a non-conducting channel at a completion of manufacturing of such device.

18. The method of claim 11 wherein said non-volatile programmable memory device is part of an array.

19. The method of claim 1, wherein a threshold voltage of said device can be set to multiple discrete levels.

20. The method of claim 1, wherein said floating gate is formed as a multi-level structure.

21. The method of claim 1, wherein said NVP device is formed as part of a thin film transistor.

22. The method of claim 1, wherein said floating gate is oriented in a non-planar configuration.

23. A method of forming a one-time programmable (OTP) memory device incorporated on a silicon substrate with one or more other additional logic and/or non-OTP memory devices, characterized in that:

a. said OTP memory device is formed with an n-type channel;

b. any and all regions and structures of said OTP memory device are formed in common with corresponding regions and structures used as components of the additional logic and/or non-OTP memory devices.

24. A method of forming a one-time programmable (OTP) memory device with a gate, an n-type impurity source and an n-type impurity drain on a silicon substrate comprising:

forming an n-type channel; and

forming the n-type impurity drain to overlap a sufficient portion of said gate such that a voltage applied to said n-type impurity drain can be imparted to said gate through capacitive coupling;

forming said gate as a floating gate so that the OTP device has a programmed state defined by a charge state of said gate.

25. A method of operating a non-volatile programmable (NVP) device situated on a substrate comprising:

providing a floating gate, which floating gate is comprised of a layer and material that is shared by gates of at least some other non-NVP devices on said substrate;

programming the NVP device to a first state with channel hot electrons that alter a voltage threshold of a floating gate;

reading the first state in the OTP device using a bias current to detect said voltage threshold; and

erasing the NVP device with band-band tunneling hot hole injection.

26. A method of operating a programmable non-volatile device comprising:

providing a floating gate;

wherein said floating gate is comprised of a material that is also used as a gate for a transistor device also situated on the substrate and associated with a logic gate and/or a volatile memory;

providing a source region; and

providing a drain region; and

providing an n-type channel coupling said source region and drain region;

capacitively coupling a portion of said gate to said drain;

providing a programming voltage to said drain, wherein a substantial portion of said programming voltage is also imparted to said floating gate through said capacitive coupling.