METHOD OF OPERATING INTEGRATED CIRCUIT EMBEDDED WITH NON-VOLATILE ONE-TIME - PROGRAMMABLE AND MULTIPLE-TIME PROGRAMMABLE MEMORY

• US 20090116295A1
• Filed: 11/03/2008
• Published: 05/07/2009
• Est. Priority Date: 11/01/2007
• Status: Active Grant

• Current Assignee: Invensas Corporation
• Original Assignee: Jonker LLC
• Inventors: Liu, David K.Y.
• Granted Patent: US 7,787,309 B2
• Time in Patent Office: Days
• US Class Current: 365/185.280
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 2216/10 Floating gate memory cells with a single polysilicon layer
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/60 the control gate being a doped region, e.g. single-poly memory cell

Abstract

A programmable non-volatile device is operated using a floating gate that functions as a FET gate that overlaps a portion of a source/drain region. This allows a programming voltage for the device to be imparted to the floating gate through capacitive coupling, thus changing the state of the device. The invention can be used in environments such as data encryption, reference trimming, manufacturing ID, security ID, and many other applications.

Claims

1. A method of operating a non-volatile programmable (NVP) device situated on a substrate comprising:

providing a floating gate, which floating gate is comprised of a layer and material that is shared by gates of at least some other non-NVP devices on said substrate;

programming the NVP device to a first state with channel hot electrons that alter a voltage threshold of a floating gate;

reading the first state in the OTP device using a bias current to detect said voltage threshold.

2. The method of claim 1 wherein said programming is done with a voltage greater than 5 volts.

3. The method of claim 1 further including a step:

erasing said floating gate.

4. The method of claim 3 wherein said erasing is done by band-band tunneling hot hole injection.

5. The method of claim 3 wherein said device can be re-programmed.

6. The method of claim 3 wherein said floating gate is eraseable by an erase voltage applied to said source region.

7. The method of claim 1 wherein a state of said floating gate can be determined by a read signal applied to said drain.

8. The method of claim 1, wherein said read signal is less than about 1 volt.

9. The method of claim 1 wherein said device is part of a programmable array embedded with separate logic circuits and/or memory circuits in an integrated circuit.

10. The method of claim 8 wherein said device is associated with one of the following:

a data encryption circuit;

a reference trimming circuit;

a manufacturing ID; and

/or a security ID.

11. The method of claim 1, wherein said capacitive coupling takes place in a first trench situated in the substrate.

12. The method of claim 10, wherein a set of second trenches in said substrate are used as embedded DRAM.

13. The method of claim 1, further including a second programmable device coupled in a paired latch arrangement such that a datum and its complement are stored in said paired latch.

14. The method of claim 1, wherein a threshold voltage of said device can be set to multiple discrete levels.

15. The method of claim 1, wherein said floating gate is a multi-level structure.

16. The method of claim 1, wherein said NVP device is part of a thin film transistor.

17. The method of claim 1, wherein said floating gate is oriented in a non-planar configuration.

18. The method of claim 1, wherein said floating gate is distributed and includes impurities acting as charge storage sites.

19. A method of operating a programmable non-volatile device comprising:

providing a floating gate;

wherein said floating gate is comprised of a material that is also used as a gate for a transistor device also situated on the substrate and associated with a logic gate and/or a volatile memory;

providing a source region; and

providing a drain region; and

providing an n-type channel coupling said source region and drain region;

capacitively coupling a portion of said gate to said drain;

providing a programming voltage to said drain, wherein a substantial portion of said programming voltage is also imparted to said floating gate through said capacitive coupling.

20. A method of operating a one-time programmable (OTP) device situated on a substrate comprising:

providing a floating gate;

wherein said floating gate is comprised of a material that is also shared by an interconnect and/or another gate for a transistor device also situated on the substrate and associated with a logic gate and/or a volatile memory;

providing a source region; and

providing a drain region overlapping a portion of said floating gate and capacitively coupled thereto; and

an n-type channel coupling said source region and drain region;

setting a threshold of said floating gate by a current of channel hot electrons to store data in the OTP device.