SEMICONDUCTOR STORAGE DEVICE

• US 20090116318A1
• Filed: 08/13/2008
• Published: 05/07/2009
• Est. Priority Date: 11/01/2007
• Status: Active Grant

• Current Assignee: Panasonic Semiconductor Solutions Co., Ltd. (Winbond Electronics Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Kuroda, Naoki
• Granted Patent: US 7,656,732 B2
• Time in Patent Office: Days
• US Class Current: 365/200
• CPC Class Codes: G11C 11/4099 Dummy cell treatment; Reference voltage generators
• CPC Class Codes: G11C 7/08 Control thereof
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators
• CPC Class Codes: G11C 7/227 Timing of memory operations based on dummy memory elements or replica circuits

Abstract

In a semiconductor storage device, such as a dynamic random access memory (DRAM), in which dynamic data is amplified and read on a bit line, a data line sense amplifier/write buffer connected to a data line of a memory array and a data line sense amplifier control signal generating logic circuit connected to a dummy data line of a dummy memory array are provided. A sense amplifier is activated in accordance with an output signal of the logic circuit.

Claims

1. A semiconductor storage device comprising:

a memory cell;

a word line and a bit line connected to the memory cell;

a first sense amplifier connected to the bit line;

a dummy memory cell;

a dummy bit line connected to the dummy memory cell;

a second sense amplifier connected to the dummy bit line;

a data line connected to the first sense amplifier;

a third sense amplifier connected to the data line;

a dummy data line connected to the second sense amplifier; and

a logic circuit connected to the dummy data line,

wherein an output signal of the logic circuit is an input signal that activates the third sense amplifier.

2. The semiconductor storage device of claim 1, wherein

the logic circuit detects that a potential on the dummy data line of static data generated by the second sense amplifier amplifying dynamic data read out to the dummy bit line exceeds a switching potential of a transistor, and outputs a signal as an input signal for activating the third sense amplifier.

3. The semiconductor storage device of claim 1, further comprising:

a latch circuit at an output of the logic circuit.

4. The semiconductor storage device of claim 1, further comprising:

a section for latching a signal on the dummy data line, the signal being input to the logic circuit, depending on a logical value of an output signal of the logic circuit.

5. The semiconductor storage device of claim 1, wherein

the memory cell and the dummy memory cell each include a transistor and a capacitor.

6. The semiconductor storage device of claim 1, wherein

a word line connected to the dummy memory cell is the same as the word line connected to the memory cell.

7. The semiconductor storage device of claim 1, wherein

the bit line and the dummy bit line are arranged in parallel with each other and the data line and the dummy data line are arranged in parallel with each other.

8. The semiconductor storage device of claim 1, wherein

the dummy memory cell is arranged adjacent to a row decoder including a word driver, and a delay circuit for adjusting output timing of the logic circuit is provided.

9. The semiconductor storage device of claim 1, wherein

adjacent capacitors of the dummy memory cells are joined together.

10. The semiconductor storage device of claim 1, wherein

a dummy memory array including the dummy memory cell, the dummy bit line and the second sense amplifier is provided for each memory array including the memory cell, the word line, the bit line and the first sense amplifier.

11. The semiconductor storage device of claim 1, wherein

the dummy memory cell includes a single transistor, and a source node of the transistor is connected to a power supply.

12. The semiconductor storage device of claim 1, wherein

two or more of the second sense amplifiers are connected to the dummy data line via switches.

13. The semiconductor storage device of claim 12, wherein

a control signal for a switch connecting the data line and the first sense amplifier is different from a control signal for a switch connecting the dummy data line and the second sense amplifier.

14. The semiconductor storage device of claim 1, wherein

the dummy data line is not a complementary line, and a line adjacent to the dummy data line is a power supply line.

17. The semiconductor storage device of claim 1, further comprising:

a redundant memory cell;

a redundant word line connected to the redundant memory cell;

a bit line connected to the redundant memory cell;

a redundant dummy memory cell; and

a dummy bit line connected to the redundant dummy memory cell.

18. The semiconductor storage device of claim 17, wherein

the logic circuit detects that a potential on the dummy data line of static data generated by the second sense amplifier amplifying dynamic data of the redundant dummy memory cell exceeds a switching potential of a transistor, and outputs a signal as an input signal for activating the third sense amplifier.

19. The semiconductor storage device of claim 1, further comprising:

a write buffer connected to the data line;

a write buffer connected to the dummy data line; and

a section for writing data to the dummy memory cell during a write operation to the memory cell.

20. The semiconductor storage device of claim 19, wherein

an input of the write buffer connected to the dummy data line is connected to a power supply or a ground potential.

21. The semiconductor storage device of claim 19, wherein

a logical value of input data of the write buffer connected to the dummy data line can be externally changed, and the logic circuit has an invariable output logic.

22. The semiconductor storage device of claim 19, further comprising:

a section for simultaneously writing data to all the dummy memory cells.

23. The semiconductor storage device of claim 19, further comprising:

a refresh counter for controlling a refresh operation;

a section for writing data to the dummy memory cell connected to the word line selected using the refresh counter.

24. The semiconductor storage device of claim 1, further comprising:

a section for reading an output of the logic circuit to the outside.

25. The semiconductor storage device of claim 24, wherein

ON/OFF of external output of the logic circuit can be switched.

26. The semiconductor storage device of claim 24, wherein

a part of or the whole pathway of data output of the memory cell is used for external output of the logic circuit.

27. The semiconductor storage device of claim 1, further comprising:

a precharge circuit for precharging the data line and the dummy data line,

wherein a precharge potential of the data line is different from a precharge potential of the dummy data line.

15. The semiconductor storage device of clam 1, wherein

the logic circuit has a function of calculating a logical sum of two or more of the dummy data lines.

16. The semiconductor storage device of claim 15, wherein

pieces of data on the two or more dummy data lines have the same logical value.