Method for Manufacturing a Trench Power Transistor

• US 20090117700A1
• Filed: 06/09/2008
• Published: 05/07/2009
• Est. Priority Date: 11/05/2007
• Status: Abandoned Application

• Current Assignee: Anpec Electronics Corporation
• Original Assignee: Anpec Electronics Corporation
• Inventors: Yeh, Jen-Hao, Lin, Wei-Chieh, Lin, Ming-Jang
• Application Number:
  US12/135,217
• Publication Number:
  US 20090117700A1
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method for manufacturing a trench power transistor includes providing a substrate, forming an epitaxy layer on the substrate, performing a dry etching process on the epitaxy layer for generating a first trench, forming a gate oxide layer in the first trench and depositing poly-Si on the gate oxide layer in the first trench, performing a boron implant process on regions outside the first trench and inside the epitaxy layer, performing an arsenic implant process on regions beside the first trench and inside the epitaxy layer, depositing a first dielectric material on the surface of the epitaxy layer, performing a dry etching process on the epitaxy layer for generating a second trench, depositing a conductive material in the second trench for forming a p-well junction on sidewalls of the second trench, and performing a wet immersion process for forming a contact hole, and depositing frontside and backside metal.

Claims

1. A method for manufacturing a trench power transistor comprising:

providing a substrate;

forming an epitaxy layer on the substrate;

performing a dry etching process on the epitaxy layer for generating a first trench;

forming a gate oxide layer in the first trench and depositing poly-Si on the gate oxide layer in the first trench;

performing a boron implant process on regions outside the first trench and inside the epitaxy layer;

performing an arsenic implant process on regions beside the first trench and inside the epitaxy layer;

depositing a first dielectric material on the surface of the epitaxy layer;

performing a dry etching process on the epitaxy layer for generating a second trench;

depositing a conductive material in the second trench for forming a p-well junction on sidewalls of the second trench; and

performing a wet immersion process for forming a contact hole, and depositing a frontside metal and a backside metal.

2. The method of claim 1, wherein performing the dry etching process on the epitaxy layer for generating the first trench is performing a Reactive Ion Etch process on the epitaxy layer for generating the first trench.

3. The method of claim 1, wherein performing the dry etching process on the epitaxy layer for generating the first trench is performing the dry etching process on the epitaxy layer for generating the first trench by a mask defining a position of the first trench.

4. The method of claim 1, wherein performing the boron implant process on the regions outside the first trench and inside the epitaxy layer comprises:

depositing boron ions into the epitaxy layer; and

performing a thermal process for driving the boron ions into the regions outside the first trench and inside the epitaxy layer, so as to form a p-body region.

5. The method of claim 1, wherein performing the arsenic implant process on the regions beside the first trench and inside the epitaxy layer comprises:

depositing arsenic ions into the epitaxy layer; and

performing a thermal process for driving the arsenic ions into the regions beside the first trench and inside the epitaxy layer, so as to form an n+ source region.

6. The method of claim 1, wherein performing the dry etching process on the epitaxy layer for generating the second trench is performing the dry etching process on the epitaxy layer for generating the second trench by a mask defining a position of the second trench.

7. The method of claim 1, wherein the material of the frontside metal is Al.

8. The method of claim 1, wherein the material of the backside metal is Ti, Ni, or Ag.