METHODS OF SELECTIVELY DEPOSITING SILICON-CONTAINING FILMS

• US 20090117717A1
• Filed: 11/05/2007
• Published: 05/07/2009
• Est. Priority Date: 11/05/2007
• Status: Active Grant

• Current Assignee: ASM IP Holding B.V. (ASM International NV)
• Original Assignee: ASM America Incorporated (ASM International NV)
• Inventors: Tomasini, Pierre, Cody, Nyles
• Granted Patent: US 7,772,097 B2
• Time in Patent Office: Days
• US Class Current: 438/488
• CPC Class Codes: C23C 16/04 Coating on selected surface areas, e.g. using masks
• CPC Class Codes: C23C 16/22 characterised by the deposition of inorganic material, other than metallic material
• CPC Class Codes: C30B 25/02 Epitaxial-layer growth
• CPC Class Codes: C30B 29/06 Silicon
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02579 P-type
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02636 Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence

Abstract

An embodiment provides a method for selectively depositing a single crystalline film. The method includes providing a substrate, which includes a first surface having a first surface morphology and a second surface having a second surface morphology different from the first surface morphology. A silicon precursor and BCl₃ are intermixed to thereby form a feed gas. The feed gas is introduced to the substrate under chemical vapor deposition conditions. A Si-containing layer is selectively deposited onto the first surface without depositing on the second surface by introducing the feed gas.

Claims

1. A method for selective depositing a single crystalline silicon film by chemical vapor deposition, the method comprising:

providing a substrate in a reaction chamber, the substrate comprising a first surface having a first surface morphology and a second surface having a second surface morphology different from the first surface morphology;

intermixing a silicon precursor with BCl₃ to thereby form a feed gas;

exposing the substrate to the feed gas in the reaction chamber; and

selectively depositing a Si-containing layer onto the first surface of the substrate without depositing on the second surface by said exposing.

2. The method of claim 1, wherein the silicon source is selected from the group consisting of silane, disilane, trisilane, tetrasilane, monochlorodisilane, dichlorodisilane, trichlorosilane, trichlorodisilane, neopentasilane, or a combination thereof.

4. The method of claim 1, further comprising intermixing the silicon precursor and BCl₃ with a halogen-containing etchant to form the feed gas.

5. The method of claim 4, wherein the halogen-containing etchant comprises HCl, and wherein intermixing the silicon precursor and BCl₃ with the etchant gas comprises flowing about 75 sccm to about 115 sccm of HCl for a single wafer CVD chamber.

6. The method of claim 1, further comprising intermixing the silicon precursor and BCl₃ with a germanium source to form the feed gas.

7. The method of claim 6, wherein the germanium source is germane, and wherein intermixing the silicon precursor and BCl₃ with the germanium source comprises flowing about 2 sccm to about 6.6 sccm of germane diluted in 10% H₂ for a single wafer CVD chamber.

8. The method of claim 1, wherein intermixing the silicon precursor and BCl₃ comprises flowing about 10 sccm to about 100 sccm of pure BCl₃ for a single wafer CVD chamber.

9. The method of claim 1, wherein the Si-containing layer comprises an in situ doped silicon film.

10. The method of claim 1, wherein the Si-containing layer comprises at least about 7×

10¹⁹ atoms cm<sup>−

3</sup> of boron as deposited.

11. The method of claim 1, wherein the Si-containing layer has a resistivity of about 1.6 mΩ

•

cm or less.

13. The method of claim 1, wherein the first surface morphology is single crystalline and wherein the second surface morphology is amorphous, polycrystalline or a mixture of amorphous and crystalline material.

14. The method of claim 1, wherein the first surface comprises a semiconductor material and the second surface comprises a dielectric material.

15. The method of claim 14, wherein the first surface comprises a source and drain region of a partially fabricated transistor.

16. The method of claim 15, wherein the first surface is recessed relative to a channel surface of the partially fabricated transistor.

17. The method of claim 15, wherein the Si-containing layer defines an elevated source/drain structure.

18. The method of claim 17, wherein the Si-containing layer introduces compressive strain into the channel region.

19. The method of claim 1, wherein the Si-containing layer comprises a heteroepitaxial film.

20. The method of claim 1, further comprising intermixing a hydrogen carrier gas to form the feed gas.

21. The method of claim 1, further comprising intermixing a non-hydrogen inert carrier gas to form the feed gas.

3. (canceled)

12. (canceled)

22. A method of forming an integrated circuit, the method comprising:

providing a substrate including exposed semiconductor surfaces and insulating regions; and

exposing the substrate to a silicon precursor, BCl₃ and an etchant vapor, thereby selectively depositing a Si-containing epitaxial film on the exposed semiconductor surfaces.

23. The method of claim 22, further comprising providing a germanium source to the substrate, so that the Si-containing film comprises a Si_1-xGe_x film, wherein 0<

x≦

1.

24. The method of claim 22, wherein the Si-containing film comprises about 15% to about 25% Ge.

25. The method of claim 22, wherein exposing selectively deposits the Si-containing film over the semiconductor surfaces while avoiding deposition over the insulating regions in a ratio of greater than about 50:

1.

26. The method of claim 22, wherein exposing selectively deposits the Si-containing film with 100% selectivity over the semiconductor surfaces while avoiding deposition over the insulating regions.

27. (canceled)

28. An apparatus configured for selective epitaxial deposition, the apparatus comprising:

a reaction chamber configured to support a substrate;

a source of semiconductor precursor in communication with the reaction chamber

a source of etchant vapor in communication with the reaction chamber;

a source of BCl₃ in communication with the reaction chamber; and

a controller configured to simultaneously deliver semiconductor precursor, etchant vapor and BCl₃ from the sources to the reaction chamber to selectively deposit an epitaxial semiconductor film on single-crystal areas of a patterned wafer in the reaction chamber.