METHODS FOR PROGRAM DIRECTED MEMORY ACCESS PATTERNS

• US 20090119443A1
• Filed: 01/06/2009
• Published: 05/07/2009
• Est. Priority Date: 08/15/2006
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Tremaine, Robert B.
• Granted Patent: US 7,636,833 B2
• Time in Patent Office: Days
• US Class Current: 711/6
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 12/10 Address translation
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

Systems and methods for program directed memory access patterns including a memory system with a memory, a memory controller and a virtual memory management system. The memory includes a plurality of memory devices organized into one or more physical groups accessible via associated busses for transferring data and control information. The memory controller receives and responds to memory access requests that contain application access information to control access pattern and data organization within the memory. Responding to memory access request includes accessing one or more memory devices. The virtual memory management system includes: a plurality of page table entries for mapping virtual memory addresses to real addresses in the memory; a hint state responsive to application access information for indicating how real memory for associated pages is to be physically organized within the memory; and a means for conveying the hint state to the memory controller.

Claims

1. A method for processing a read request in a memory system, the method comprising:

receiving a read request including a virtual address;

completing a virtual address to real address mapping;

forwarding the real address to a memory controller that is in communication with a plurality of busses;

selecting one or more of the busses that are required to process the read request;

accessing just the required busses to process the read request;

reading data responsive to the read request from one or more memory devices attached to the required busses; and

transmitting the data to a requestor.

2. The method of claim 1 further comprising performing an ECC check on just the required busses.

3. The method of claim 1 wherein the selecting is responsive to an access hint associated with the virtual address.

4. The method of claim 1 wherein two or more memory access requests are processed concurrently by the memory system via the busses.

5. A method for processing a write request in a memory system, the method comprising:

receiving a write request including application access information at a memory controller that is in communication with a plurality of busses;

selecting one or more of the busses that are required to process the write request, the selecting responsive to the application access information;

accessing just the required busses to process the write request; and

writing data responsive to the write request to one or more memory devices attached to the required busses.

6. The method of claim 5 further comprising creating an ECC code for just the busses required to process the write request.

7. The method of claim 5 further comprising processing one or more of a read request that requires a different set of busses than the write request or a second write request that requires a different set of busses than the write request in parallel with the write request.