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Computer memory architecture for hybrid serial and parallel computing systems

  • US 20090119481A1
  • Filed: 11/29/2006
  • Published: 05/07/2009
  • Est. Priority Date: 11/29/2005
  • Status: Active Grant
First Claim
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1. An apparatus comprising:

  • a serial processor adapted to execute software instructions in a software program primarily in serial;

    a serial memory adapted to store data for use by the serial processor in executing the software instructions primarily in serial;

    a plurality of parallel processors adapted to execute software instructions in the software program primarily in parallel; and

    a plurality of partitioned memory modules adapted to store data for use by the plurality of parallel processors in executing the software instructions primarily in parallel;

    wherein the serial processor is further adapted, prior to a transition from a serial processing mode to a parallel processing mode, to provide for a transfer of updated data from the serial memory to at least one of the plurality of partitioned memory modules and to receive a corresponding acknowledgement from the at least one of the plurality of partitioned memory modules that the updated data has been queued or committed prior to any memory requests from the plurality of parallel processors.

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