Computer memory architecture for hybrid serial and parallel computing systems
First Claim
1. An apparatus comprising:
- a serial processor adapted to execute software instructions in a software program primarily in serial;
a serial memory adapted to store data for use by the serial processor in executing the software instructions primarily in serial;
a plurality of parallel processors adapted to execute software instructions in the software program primarily in parallel; and
a plurality of partitioned memory modules adapted to store data for use by the plurality of parallel processors in executing the software instructions primarily in parallel;
wherein the serial processor is further adapted, prior to a transition from a serial processing mode to a parallel processing mode, to provide for a transfer of updated data from the serial memory to at least one of the plurality of partitioned memory modules and to receive a corresponding acknowledgement from the at least one of the plurality of partitioned memory modules that the updated data has been queued or committed prior to any memory requests from the plurality of parallel processors.
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Accused Products
Abstract
In one embodiment, a serial processor is configured to execute software instructions in a software program in serial. A serial memory is configured to store data for use by the serial processor in executing the software instructions in serial. A plurality of parallel processors are configured to execute software instructions in the software program in parallel. A plurality of partitioned memory modules are provided and configured to store data for use by the plurality of parallel processors in executing software instructions in parallel. Accordingly, a processor/memory structure is provided that allows serial programs to use quick local serial memories and parallel programs to use partitioned parallel memories. The system may switch between a serial mode and a parallel mode. The system may incorporate pre-fetching commands of several varieties. For example, towards switching between the serial mode and the parallel mode, the serial processor is configured to send a signal to start pre-fetching of data from the shared memory.
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Citations
39 Claims
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1. An apparatus comprising:
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a serial processor adapted to execute software instructions in a software program primarily in serial; a serial memory adapted to store data for use by the serial processor in executing the software instructions primarily in serial; a plurality of parallel processors adapted to execute software instructions in the software program primarily in parallel; and a plurality of partitioned memory modules adapted to store data for use by the plurality of parallel processors in executing the software instructions primarily in parallel;
wherein the serial processor is further adapted, prior to a transition from a serial processing mode to a parallel processing mode, to provide for a transfer of updated data from the serial memory to at least one of the plurality of partitioned memory modules and to receive a corresponding acknowledgement from the at least one of the plurality of partitioned memory modules that the updated data has been queued or committed prior to any memory requests from the plurality of parallel processors. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. An apparatus comprising:
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a serial processor adapted to execute software instructions in a software program primarily in serial; a serial memory adapted to store data for use by the serial processor in executing the software instructions in serial; a plurality of parallel processors adapted to execute software instructions in the software program primarily in parallel; and a plurality of partitioned memory modules configured to store data for use by the plurality of parallel processors in executing the software instructions primarily in parallel; wherein the serial processor is further adapted, prior to a transition from a serial processing mode to a parallel processing mode, to broadcast a prefetching signal to the plurality of parallel processors to initiate prefetching of data from at least a portion of the plurality of partitioned memory modules. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31)
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32. An apparatus comprising:
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an interconnection network; a plurality of parallel processors coupled to the interconnection network and adapted to execute software instructions in the software program substantially in parallel; a plurality of partitioned memory modules coupled to the interconnection network and adapted to store data for use by the plurality of parallel processors in executing the software instructions substantially in parallel; a broadcast network coupled to the plurality of parallel processors; a serial processor coupled to the broadcast network and adapted to execute software instructions in a software program primarily in serial; and a serial memory coupled to the interconnection network and adapted to store data for use by the serial processor in executing the software instructions substantially in serial; wherein the serial processor is further adapted, prior to a transition from a serial processing mode to a parallel processing mode, to provide for a transfer of updated data from the serial memory to the plurality of partitioned memory modules, to receive corresponding acknowledgements from the plurality of partitioned memory modules that the updated data has been queued or committed prior to any memory requests from the plurality of parallel processors, and to broadcast a prefetching signal to the plurality of parallel processors to initiate prefetching of data from at least a portion of the plurality of partitioned memory modules.
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33. A method of transitioning from a serial processing mode to a parallel processing mode in a computing system, the method comprising:
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transferring updated data from a serial memory to at least one of a plurality of partitioned memory modules; receiving a corresponding acknowledgement from the at least one of the plurality of partitioned memory modules that the updated data has been queued or committed to be stored in memory, prior to any memory requests from the plurality of parallel processors; broadcasting a first signal to the plurality of parallel processors to initiate prefetching of data from at least a portion of the plurality of partitioned memory modules; and broadcasting a second signal to the plurality of parallel processors for substantially concurrent initiation of a parallel processing mode. - View Dependent Claims (34, 35, 36, 37, 38, 39)
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Specification