Structure for System Architectures for and Methods of Scheduling On-Chip and Across-Chip Noise Events in an Integrated Circuit

• US 20090119625A1
• Filed: 11/05/2007
• Published: 05/07/2009
• Est. Priority Date: 11/05/2007
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Twombly, Peter A., Goodnow, Kenneth J., Zuchowski, Paul S., Barrows, Corey K., Shuma, Stephen G.
• Granted Patent: US 7,949,978 B2
• Time in Patent Office: Days
• US Class Current: 716/115
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist

Abstract

A design structure integrated circuit (IC) system architectures that allow for the reduction of on-chip or across-chip transient noise budgets by providing a means to avoid simultaneous high current demand events from at least two functional logic blocks, i.e., noise contributors, are disclosed. Embodiments of the IC system architectures include at least one noise event arbiter and at least two noise contributor blocks. A method of scheduling on-chip noise events to avoid simultaneous active transient noise events may include, but is not limited to: the noise event arbiter receiving simultaneously multiple requests-to-operate from multiple noise contributors; the noise event arbiter determining when each noise contributor may execute operations based on a pre-established dI/dt budget; and the noise event arbiter notifying each noise contributor as to when permission is granted to execute its operations.

Claims

1. A design structure embodied in a machine readable medium used in a design process for an integrated circuit device, the design structure for said integrated circuit device comprising:

an integrated circuit having a predetermined instantaneous current draw threshold and including;

a first functional block provided to perform at least one first predefined operation and including a first request-to-operate signal generator configured to generate a first request-to-operate signal; and

a second functional block provided to perform at least one second predefined operation and including a second request-to-operate signal generator configured to generate a second request-to-operate signal; and

a noise arbiter in communication with each of said first functional block and said second functional block, said noise arbiter controlling when each of said first functional block and said second functional block will operate as a function of said first request-to-operate signal, said second request-to-operate signal and said predetermined instantaneous current draw threshold.

2. The design structure of claim 1, wherein the design structure comprises a netlist, which describes the circuit.

3. The design structure of claim 1, wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits.

4. The design structure of claim 1, wherein the design structure includes at least one of test data files, characterization data, verification data, or design specifications.

5. A design structure embodied in a machine readable medium for performing a method of controlling instantaneous current noise in an integrated circuit having a predetermined instantaneous current draw threshold and that includes a plurality of noise contributors each configured to generate a request-to-operate signal and each configured to perform at least one predefined operation, the design structure comprising:

a means for receiving substantially simultaneously a plurality of request-to-operate signals from corresponding ones of the plurality of noise contributors;

a means for determining when ones of the plurality of predefined operations corresponding to said corresponding ones of the plurality of noise contributors execute relative to one another as a function of the predetermined instantaneous current draw threshold and a pre-determined priority scheme; and

a means for notifying each of said corresponding ones of the plurality of noise contributors to perform the corresponding at least one predefined operation in accordance with the preceding determining step.