Virtual heterogeneous channel for message passing

• US 20090119676A1
• Filed: 10/31/2008
• Published: 05/07/2009
• Est. Priority Date: 09/27/2006
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Supalov, Alexander V., Truschin, Vladimir D., Ryzhykh, Alexey V.
• Granted Patent: US 7,949,815 B2
• Time in Patent Office: Days
• US Class Current: 719/312
• CPC Class Codes: G06F 9/544 Buffers; Shared memory; Pipes

Abstract

A technique includes using a virtual channel between a first process and a second process to communicate messages between the processes. Each message contains protocol data and user data. All of the protocol data is communicated over a first channel associated with the virtual channel, and the user data is selectively communicated over at least one other channel associated with the virtual channel.

Claims

1. A method comprising:

creating a shared memory segment to store a synchronization block for each process to execute in a message passing interface (MPI) library, wherein each synchronization block includes a wait flag to indicate that the associated process is in a wait state and a wake up counter to indicate a number of messages sent by the associated process to another process that have not been received;

transferring a message from a first process to a shared memory buffer of a second process via a shared memory connection; and

sending a wake up message from the first process to the second process via a secondary connection if the second process is in the wait state.

2. The method of claim 1, further comprising moving the message from the shared memory buffer to a user buffer of the second process.

3. The method of claim 2, further comprising sending a wake up message from the second process to the first process if the first process is in the wait state when the second process moves the message.

4. The method of claim 3, further comprising de-allocating the shared memory buffer via the first process after the first process is activated from the wait state.

5. The method of claim 1, further comprising determining that the second process is in the wait state by analysis of the corresponding synchronization block.

6. The method of claim 5, where the analysis includes checking the wait flag of the corresponding synchronization block and sending the wake up message if the wait flag indicates that the second process is in the wait state and the wake up counter is equal to zero.

7. The method of claim 1, further comprising creating an intranode heterogeneous virtual channel between the first process and the second process in a wait mode.

8. The method of claim 7, further comprising creating the intranode heterogeneous virtual channel through a shared memory and through a second communication fabric.

9. The method of claim 8, further comprising communicating a location of the shared memory segment to a plurality of processes across the MPI library using an out-of-band communication channel.

10. An article comprising a machine-accessible storage medium including instructions that when executed cause a system to:

prepare a message to be sent from a first process to a second process via a remote direct memory access (RDMA) write operation, the message including user data and immediate data to indicate a type of the user data; and

send the message from the first process to the second process using the RDMA write operation.

11. The article of claim 10, further comprising instructions that enable the system to determine the type of user data and to copy eager data into an internal buffer if the type of user data is eager data.

12. The article of claim 10, wherein the second process is in a wait mode when the message is sent.

13. The article of claim 12, further comprising instructions that enable the system to, during initialization, create an event dispatcher of the second process to handle completion of a received RDMA write operation when the second process is in the wait mode.

14. The article of claim 13, wherein the immediate data of the message is sent within an event structure for the event dispatcher of the second process.

15. The article of claim 14, further comprising instructions that enable the system to determine that transfer of the message has been completed using the event dispatcher of the second process.

16. The article of claim 10, further comprising instructions that enable the system to determine the type of user data and handle the user data based on the type of data.

17. The article of claim 16, further comprising instructions that enable the system to copy the user data from an internal buffer to a user buffer if the type of data is eager data.

18. A system comprising:

a first processor to send a message from a first process executing on the first processor to a second process executing on a second processor, wherein the first process is to send the message while the second process is in a wait state;

the second processor to receive the message from the first process while the second process is in the wait state, wherein the first process is to initiate a wake up message to the second process if the second process is in the wait state when the message is sent; and

a dynamic random access memory (DRAM) coupled to the first and second processors.

19. The system of claim 18, wherein the DRAM includes instructions to create a shared memory segment to store a synchronization block for the first and second processes, wherein each synchronization block includes a wait flag to indicate that the associated process is in the wait state and a wake up counter to indicate a number of messages sent by the associated process to another process that have not been received.

20. The system of claim 19, wherein the first process is to check the wait flag of the corresponding synchronization block and send the wake up message if the wait flag indicates that the second process is in the wait state and the wake up counter is equal to zero, and to send the message via a shared memory buffer and to send the wake up message via a secondary connection.