Wire bond free wafer level LED

• US 20090121241A1
• Filed: 11/14/2007
• Published: 05/14/2009
• Est. Priority Date: 11/14/2007
• Status: Active Grant

• Current Assignee: Creeled Incorporated
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Batres, Max, Ibbetson, James, Keller, Bernd, Medendorp, Nicholas W. JR., Chitnis, Ashay
• Granted Patent: US 9,634,191 B2
• Time in Patent Office: Days
• US Class Current: 257/96
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/45139 Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/49107 on the semiconductor or solid-state body
• CPC Class Codes: H01L 25/0756 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/207 Diameter ranges
• CPC Class Codes: H01L 33/08 with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body H01L27/15 takes precedence
• CPC Class Codes: H01L 33/22 Roughened surfaces, e.g. at the interface between epitaxial layers
• CPC Class Codes: H01L 33/385 the electrode extending at least partially onto a side surface of the semiconductor body
• CPC Class Codes: H01L 33/46 Reflective coating, e.g. dielectric Bragg reflector
• CPC Class Codes: H01L 33/486 adapted for surface mounting
• CPC Class Codes: H01L 33/50 Wavelength conversion elements
• CPC Class Codes: H01L 33/505 characterised by the shape, e.g. plate or foil
• CPC Class Codes: H01L 33/58 Optical field-shaping elements
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

A wire-bond free semiconductor device with two electrodes both of which are accessible from the bottom side of the device. The device is fabricated with two electrodes that are electrically connected to the oppositely doped epitaxial layers, each of these electrodes having leads with bottom-side access points. This structure allows the device to be biased with an external voltage/current source, obviating the need for wire-bonds or other such connection mechanisms that must be formed at the packaging level. Thus, features that are traditionally added to the device at the packaging level (e.g., phosphor layers or encapsulants) may be included in the wafer level fabrication process. Additionally, the bottom-side electrodes are thick enough to provide primary structural support to the device, eliminating the need to leave the growth substrate as part of the finished device.

Claims

1. A semiconductor device comprising:

an n-type semiconductor layer;

a p-type semiconductor layer;

an active region interposed between said n-type and p-type layers;

a p-electrode having a lead that is accessible on a surface opposite of a primary emission surface of said semiconductor device, said p-electrode electrically connected to said p-type layer; and

an n-electrode having a lead that is also accessible on a surface opposite of said primary emission surface, said n-electrode electrically connected to said n-type layer;

wherein said p-electrode and said n-electrode are thick enough to provide primary mechanical support for said semiconductor device.

2. The semiconductor device of claim 1, further comprising:

an n-pad contacting said n-type layer and providing an electrical connection between said -n-type layer and said n-electrode; and

a p-pad contacting said p-type layer and providing an electrical connection between said p-type layer and said p-electrode.

3. The semiconductor device of claim 2, wherein said n-pad partially overlaps said p-pad, said n- and p-pads electrically isolated by a spacer element.

4. The semiconductor device of claim 2, wherein said p-pad partially overlaps said n-pad, said p- and n-pads electrically isolated by a spacer element.

5. The semiconductor device of claim 2, wherein said p-pad comprises a reflective material.

6. The semiconductor device of claim 1, further comprising a phosphor layer disposed opposite said leads of said n- and p-electrodes such that said phosphor layer comprises said primary emitting surface.

7. The semiconductor device of claim 6, wherein said phosphor layer is disposed on said n-type layer.

8. The semiconductor device of claim 6, wherein said phosphor layer is disposed on said p-type layer.

9. The semiconductor device of claim 8, further comprising a current spreading layer interposed between said phosphor layer and said p-type layer, said current spreading layer electrically connected to said p-electrode.

10. The semiconductor device of claim 1, further comprising at least one spacer element arranged to electrically isolate said n-electrode from said p-electrode and to electrically isolate both said n- and p-electrodes from said active region.

11. The semiconductor device of claim 10, wherein said at least one spacer element comprises a dielectric material.

12. The semiconductor device of claim 10, wherein said at least one spacer element comprises a polymer.

13. The semiconductor device of claim 1, wherein said n-type layer comprises a modified surface.

14. The semiconductor device of claim 1, wherein substantially all of said n-type layer, said active region and said p-type layer are disposed above said p-electrode.

15. The semiconductor device of claim 14, wherein the top lateral surface of said n-type layer is electrically connected to said n-electrode with a stairstep-shaped n-pad.

16. The semiconductor device of claim 1, wherein said n-type layer, said p-type layer and said active region comprise materials from the Group-III Nitrides.

17. The semiconductor device of claim 1, wherein the thickness of said p-electrode is at least 20 μ

m and the thickness of said n-electrode is at least 20 μ

m.

18. The semiconductor device of claim 1, wherein the thickness of said p-electrode is at least 50 μ

m and said n-electrode is at least 50 μ

m.

19. The semiconductor device of claim 1, wherein substantially all of said n-type layer, said active region and said p-type layer are disposed between said n-electrode and said primary emission surface.

20. A semiconductor device having top and bottom surfaces, comprising:

a base element thick enough to provide structural support for said semiconductor device;

a first semiconductor layer;

a second semiconductor layer disposed on said base element;

an active region interposed between said first and second semiconductor layers;

a first electrode electrically contacting said first semiconductor layer and having a lead that is accessible from said bottom surface, wherein said first electrode is disposed substantially perpendicular to said bottom surface and extends from the top of said first semiconductor layer to said bottom surface of the device; and

a first spacer layer disposed to isolate said first electrode from said second semiconductor layer and said base element.

21. The semiconductor device of claim 20, wherein said base element comprises a substrate.

22. The semiconductor device of claim 20, wherein said base element comprises an electrically conductive material, said conductive material electrically contacting said second semiconductor layer, said conductive material constituting a portion of said bottom surface.

23. The semiconductor device of claim 20, wherein said base element comprises a metal or metal alloy material.

24. The semiconductor device of claim 20, wherein said base element provides an electrical connection to said second semiconductor layer.

25. The semiconductor device of claim 20, further comprising:

a second electrode electrically contacting said second semiconductor layer and having a lead that is accessible from said bottom surface, wherein said second electrode is disposed substantially perpendicular to said bottom surface; and

a second spacer layer disposed to isolate said second electrode from said first semiconductor layer and said base element.

26. The semiconductor device of claim 20, further comprising a phosphor layer disposed over said first semiconductor layer, said phosphor layer constituting at least a portion of said top surface of said semiconductor device.

27. The semiconductor device of claim 26, further comprising a current spreading layer disposed over said first semiconductor layer, said current spreading layer contacting said first semiconductor layer and said first electrode and providing an electrical path there between.

28. The semiconductor device of claim 20, further comprising a reflective layer disposed to redirect light emitted from said active region toward said top surface of said semiconductor device.

29. The semiconductor device of claim 28, wherein said reflective layer is disposed on the bottom surface of said base element opposite said second semiconductor layer.

30. The semiconductor device of claim 28, wherein said reflective layer is interposed between said base element and said second semiconductor layer.

31. The semiconductor device of claim 20, further comprising at least one modified surface, said modified surface structured to increase light extraction from said semiconductor device.

32. The semiconductor device of claim 31, wherein said first semiconductor layer comprises a modified surface.

33. The semiconductor device of claim 31, wherein said second semiconductor comprises a modified surface.

34. The semiconductor device of claim 31, wherein said modified surface has been textured.

35. The semiconductor device of claim 20, wherein said first semiconductor layer comprises a p-type layer and said second semiconductor layer comprises an n-type layer.

36. The semiconductor device of claim 20, wherein said first semiconductor layer comprises an n-type layer and said second semiconductor layer comprises a p-type layer.

37. The semiconductor device of claim 20, wherein said semiconductor layers and said active region comprise materials from the Group III-Nitrides.

38. The semiconductor device of claim 20, wherein said base element has a thickness of at least 20 μ

m.

39. The semiconductor device of claim 20, wherein said base element has a thickness of at least 50 μ

m.

40. A method for fabricating semiconductor devices comprising:

providing a growth substrate;

growing a first semiconductor layer on said growth substrate;

growing an active region on said first semiconductor layer;

growing a second semiconductor layer on said active region opposite said first semiconductor layer;

exposing a portion of said first semiconductor layer opposite said growth substrate;

forming a spacer layer on said second semiconductor layer and said exposed portion of said first semiconductor layer;

removing a portion of said spacer layer such that a portion of said first and second semiconductor layers is exposed;

forming an electrode layer on the remaining portions of said spacer layer and the exposed portions of said first and second semiconductor layers;

removing said growth substrate; and

removing a portion of said electrode layer to form first and second electrodes such that said first electrode is electrically contacting said first semiconductor layer and said second electrode is electrically contacting said second semiconductor layer, said first and second electrodes disposed to be electrically isolated from one another and from said active region.

41. The method of claim 40, further comprising modifying at least one internal surface such that the structure of the surface increases light extraction from said semiconductor devices.

42. The method of claim 40, further comprising forming a reflective layer on a surface of said first semiconductor layer opposite said active region.

43. The method of claim 40, further comprising forming a phosphor layer on said second semiconductor layer.

44. A semiconductor device, comprising:

an n-type semiconductor layer;

a p-type semiconductor layer having at least one via;

an active region interposed between said n-type and p-type layers, said active region having at least one via corresponding to said at least one via in said p-type layer, such that a portion of said n-type layer adjacent to said active region is exposed;

at least one p-electrode having a lead that is accessible on a surface opposite of a primary emission surface of said semiconductor device, said at least one p-electrode electrically connected to said p-type layer; and

at least one n-electrode having a lead that is accessible on a surface opposite of said primary emission surface, said at least one n-electrode electrically connected to said n-type layer;

wherein said at least one p-electrode and said at least one n-electrode are thick enough to provide primary mechanical support for said semiconductor device.

45. The semiconductor device of claim 44, wherein the device is scalable.

46. The semiconductor device of claim 44, further comprising:

an n-pad contacting said n-type layer in a plurality of locations and through said vias, said n-pad providing an electrical connection between said n-type layer and said n-electrode; and

a p-pad contacting said p-type layer, said p-pad having at least one via that corresponds with said at least one via in said p-type layer, and said p-pad providing an electrical connection between said p-type layer and said p-electrode.

47. The semiconductor device of claim 46, wherein the electrical path from said at least one n-electrode to said n-type layer is confined by insulating spacer elements.

48. The semiconductor device of claim 46, wherein the electrical path from said at least one p-electrode to said p-type layer is confined by insulating spacer elements.

49. The semiconductor of claim 46, wherein said n-pad at least partially overlaps said p-pad, said n- and p-pads electrically isolated by a spacer element.

50. The semiconductor of claim 46, wherein said p-pad at least partially overlaps said n-pad, and said p- and n-pads are electrically isolated by at least one spacer element.

51. The semiconductor device of claim 46, wherein said p-pad comprises a reflective material.

52. The semiconductor device of claim 46, wherein said p-pad comprises at least one transparent conductive oxide layer.

53. The semiconductor device of claim 46, wherein said p-pad comprises a reflective multilayer stack of transparent materials with different refractive indices.

54. The semiconductor device of claim 46, wherein said n-pad comprises a reflective material.

55. The semiconductor device of claim 44, further comprising a phosphor layer disposed opposite said leads of said n- and p-electrodes such that said phosphor layer comprises said primary emitting surface.

56. The semiconductor of claim 44, wherein said n-type layer comprises a modified surface structured to increase light extraction.

57. The semiconductor device of claim 44, wherein said n-type layer, said p-type layer and said active region comprise materials from the Group-III Nitrides.

58. The semiconductor device of claim 44, wherein the thickness of said at least one p-electrode is at least 20 μ

m and the thickness of said at least one n-electrode is at least 20 μ

m.

59. The semiconductor device of claim 44, wherein the thickness of said at least one p-electrode is at least 50 μ

m and the thickness of said at least one n-electrode is at least 50 μ

m.