DENSE CHEVRON NON-PLANAR FIELD EFFECT TRANSISTORS AND METHOD

• US 20090121291A1
• Filed: 11/14/2007
• Published: 05/14/2009
• Est. Priority Date: 11/14/2007
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Nowak, Edward J., Anderson, Brent A., Bryant, Andres
• Granted Patent: US 7,847,320 B2
• Time in Patent Office: Days
• US Class Current: 257/365
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Disclosed are embodiments of semiconductor structure and a method of forming the semiconductor structure that simultaneously maximizes device density and avoids contacted-gate pitch and fin pitch mismatch, when multiple parallel angled fins are formed within a limited area on a substrate and then traversed by multiple parallel gates (e.g., in the case of stacked, chevron-configured, CMOS devices). This is accomplished by using, not a minimum lithographic fin pitch, but rather by using a fin pitch that is calculated as a function of a pre-selected contacted-gate pitch, a pre-selected fin angle and a pre-selected periodic pattern for positioning the fins relative to the gates within the limited area. Thus, the disclosed structure and method allow for the conversion of a semiconductor product design layout with multiple, stacked, planar FETs in a given area into a semiconductor product design layout with multiple, stacked, chevron-configured, non-planar FETs in the same area.

Claims

1. An integrated circuit structure comprising:

a substrate;

multiple parallel angled semiconductor fins on said substrate within a limited area; and

multiple parallel gates on said substrate within said limited area,

wherein said gates intersect said fins and have a pre-selected first pitch,

wherein said fins are positioned relative to said gates at a pre-selected angle and according to a pre-selected periodic pattern that repeats within said limited area at every gate and with every fin, and

wherein said fins further have a second pitch that is predetermined, based on said angle and said first pitch, in order to achieve said periodic pattern.

2. The structure according to claim 1, all the limitations of which are incorporated herein by reference, wherein said second pitch is approximately equal to said first pitch multiplied by the cosine of said angle.

3. The structure according to claim 1, all the limitations of which are incorporated herein by reference, wherein said angle is other than 90 degrees.

4. The structure according to claim 1, all the limitations of which are incorporated herein by reference, wherein said limited area comprises a rectangular-shaped area.

5. An integrated circuit structure comprising:

a substrate;

multiple parallel angled semiconductor fins on said substrate within a limited area; and

multiple parallel gates on said substrate within said limited area,

wherein said gates intersect said fins and have a pre-selected first pitch,

wherein said fins are positioned relative to said gates at a pre-selected angle and according to a pre-selected periodic pattern,

wherein said pre-selected periodic pattern repeats within said limited area at every Nth gate and at every Mth fin, and

wherein said fins further have a second pitch that is predetermined, based on said angle, a ratio of N over M, and said first pitch, in order to achieve said periodic pattern.

6. The structure according to claim 5, all the limitations of which are incorporated herein by reference, wherein said second pitch is approximately equal to said ratio of N/M multiplied by said first pitch multiplied by the cosine of said angle.

7. The structure according to claim 5, all the limitations of which are incorporated herein by reference, wherein said angle is other than 90 degrees.

8. The structure according to claim 5, all the limitations of which are incorporated herein by reference, wherein said limited area comprises a rectangular-shaped area.

9. A method of forming an integrated circuit structure:

providing a substrate;

designating a limited area of said substrate for subsequent formation of multiple parallel angled semiconductor fins and for formation of multiple parallel gates that will intersect said fins;

pre-selecting a first pitch between said gates;

pre-selecting an angle of intersection between said fins and said gates;

pre-selecting a periodic pattern for positioning said fins relative to said gates within said limited area such that said periodic pattern repeats within said limited area at every gate and with every fin;

based on said angle and said first pitch, calculating a second pitch required between said fins in order to achieve said periodic pattern; and

forming said fins with said second pitch and said gates with said first pitch within said limited area such that fins are positioned with said periodic pattern and at said angle relative to said gates.

10. The method according to claim 9, all the limitations of which are incorporated herein by reference, wherein said calculating comprises solving for:

P_fins=P_gates×

cos B, where P_fins comprises said second pitch, P_gates comprises said first pitch and B comprises said angle.

11. The method according to claim 9, all the limitations of which are incorporated herein by reference, wherein said angle is other than 90 degrees.

12. The method according to claim 9, all the limitations of which are incorporated herein by reference, wherein said angle is approximately 67.5 degrees.

13. The method according to claim 9, all the limitations of which are incorporated herein by reference, wherein said limited area comprises a rectangular-shaped area.

14. The method according to claim 9, all the limitations of which are incorporated herein by reference, wherein said pre-selecting of said first pitch comprises determining a currently achievable minimum lithographic gate pitch,

wherein said pre-selecting of said angle comprises pre-selecting said angle based on a desired crystalline orientation, and

wherein said pre-selecting of said periodic pattern further comprises pre-selecting said periodic pattern such that said periodic pattern is sufficient to convert a first design layout that comprises planar field effect transistors within said limited area to a second design layout that comprises non-planar field effect transistors within said limited area.

15. A method of forming an integrated circuit structure:

providing a substrate;

designating a limited area of said substrate for subsequent formation of multiple parallel angled semiconductor fins and for formation of multiple parallel gates that will intersect said fins;

pre-selecting a first pitch between said gates;

pre-selecting an angle of intersection between said fins and said gates;

pre-selecting a periodic pattern for positioning said fins relative to said gates within said limited area, wherein said pre-selecting of said periodic pattern comprises;

choosing a first number N such that said periodic pattern repeats within said limited area at every Nth gate; and

choosing a second number M such that said periodic pattern further repeats within said limited area at every Mth fin;

based on said angle, a ratio of said first number N over said second number M, and said first pitch, calculating a second pitch required between said fins in order to achieve said periodic pattern;

forming said fins with said second pitch and said gates with said first pitch within said limited area such that fins are positioned with said periodic pattern and at said angle relative to said gates.

16. The method according to claim 15, all the limitations of which are incorporated herein by reference, wherein said calculating comprises solving for:

P_fins=N/M(P_gates×

cos B), where P_fins comprises said second pitch, P_gates comprises said first pitch and B comprises said angle.

17. The method according to claim 15, all the limitations of which are incorporated herein by reference, wherein said angle is other than 90 degrees.

18. The method according to claim 15, all the limitations of which are incorporated herein by reference, wherein said limited area comprises a rectangular-shaped area.

19. The method according to claim 15, all the limitations of which are incorporated herein by reference, wherein said pre-selecting of said first pitch comprises determining a currently achievable minimum lithographic gate pitch,

wherein said pre-selecting of said angle comprises pre-selecting said angle based on a desired crystalline orientation, and

wherein said pre-selecting of said periodic pattern further comprises pre-selecting said periodic pattern such that said periodic pattern is sufficient to convert a first design layout that comprises planar field effect transistors within said limited area to a second design layout that comprises non-planar field effect transistors within said limited area.

20. The method according to claim 15, all the limitations of which are incorporated herein by reference, wherein said choosing of said first number N and choosing of said second number M comprise choosing said first number N and said second number M such that said calculating of said second pitch will result in pitch value at least as great as a currently achievable minimum lithographic fin pitch.