Chip Package

• US 20090121302A1
• Filed: 01/13/2009
• Published: 05/14/2009
• Est. Priority Date: 06/06/2005
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Lin, Shih-Hsiung, Lo, Hsin-Jung
• Granted Patent: US 8,044,475 B2
• Time in Patent Office: Days
• US Class Current: 257/432
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14683 Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof not peculiar thereto H01L21/00
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 31/0203 Containers; Encapsulations , e.g. encapsulation of photodiodesfor photovoltaic devices H01L31/048; for organic photosensitive devices H10K30/80
• CPC Class Codes: H01L 31/18 Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof

Abstract

A chip package includes a bump connecting said semiconductor chip and said circuitry component, wherein the semiconductor chip has a photosensitive area used to sense light. The chip package may include a ring-shaped protrusion connecting a transparent substrate and the semiconductor chip.

Claims

1. A chip package comprising:

a semiconductor chip comprising a CMOS device, a passivation layer over said CMOS device, wherein said passivation layer comprises a nitride layer, a metal pad having a contact point at a bottom of an opening in said passivation layer, wherein said opening is over said contact point, an optical filter over said passivation layer and over said CMOS device, and a microlens over said optical filter, over said passivation layer and over said CMOS device;

a metal bump on said semiconductor chip, wherein said metal bump is connected to said contact point through said opening, and wherein said metal bump comprises an electroplated gold layer having a thickness between 1 and 50 micrometers;

a transparent substrate over said semiconductor chip; and

a spacer between said semiconductor chip and said transparent substrate, wherein said spacer has a bottom end joined with said semiconductor chip and a top end joined with said transparent substrate, and wherein said spacer from a top perspective view is between said microlens and said metal bump.

2. The chip package of claim 1, wherein said metal bump further comprises a titanium-containing layer on said contact point and a gold seed layer on said titanium-containing layer, wherein said electroplated gold layer is on said gold seed layer.

3. The chip package of claim 1, wherein said spacer comprises a polymer.

4. The chip package of claim 1 further comprising a flexible tape joined with said metal bump, wherein said metal bump is further between said flexible tape and said semiconductor chip.

5. The chip package of claim 1, wherein said spacer comprises an electroplated gold layer having a thickness between 1 and 50 micrometers.

6. The chip package of claim 1, wherein said transparent substrate comprises glass.

7. The chip package of claim 1, wherein said nitride layer has a thickness between 0.2 and 0.7 micrometers.

8. The chip package of claim 1, wherein said passivation layer further comprises an oxide layer under said nitride layer.

9. A chip package comprising:

a semiconductor chip comprising a CMOS device, a passivation layer over said CMOS device, wherein said passivation layer comprises a nitride layer, a metal pad having a contact point at a bottom of an opening in said passivation layer, wherein said opening is over said contact point, an optical filter over said passivation layer and over said CMOS device, and a microlens over said optical filter, over said passivation layer and over said CMOS device;

a metal bump on said semiconductor chip, wherein said metal bump is connected to said contact point through said opening, and wherein said metal bump comprises an electroplated copper layer having a thickness between 1 and 100 micrometers;

a transparent substrate over said semiconductor chip; and

a spacer between said semiconductor chip and said transparent substrate, wherein said spacer has a bottom end joined with said semiconductor chip and a top end joined with said transparent substrate, and wherein said spacer from a top perspective view is between said microlens and said metal bump.

10. The chip package of claim 9, wherein said metal bump further comprises an adhesion/barrier layer on said contact point and a copper seed layer on said adhesion/barrier layer, wherein said electroplated copper layer is on said copper seed layer.

11. The chip package of claim 9, wherein said spacer comprises a polymer.

12. The chip package of claim 9 further comprising a flexible tape joined with said metal bump, wherein said metal bump is further between said flexible tape and said semiconductor chip.

13. The chip package of claim 9, wherein said transparent substrate comprises glass.

14. The chip package of claim 9, wherein said nitride layer has a thickness between 0.2 and 0.7 micrometers.

15. The chip package of claim 9, wherein said passivation layer further comprises an oxide layer under said nitride layer.

16. A chip package comprising:

a semiconductor chip comprising a CMOS device, a passivation layer over said CMOS device, wherein said passivation layer comprises a nitride layer, a metal pad having a contact point at a bottom of an opening in said passivation layer, wherein said opening is over said contact point, an optical filter over said passivation layer and over said CMOS device, and a microlens over said optical filter, over said passivation layer and over said CMOS device;

a metal bump on said semiconductor chip, wherein said metal bump is connected to said contact point through said opening, and wherein said metal bump comprises a tin-containing layer having a thickness between 1 and 300 micrometers;

a transparent substrate over said semiconductor chip; and

a spacer between said semiconductor chip and said transparent substrate, wherein said spacer has a bottom end joined with said semiconductor chip and a top end joined with said transparent substrate, and wherein said spacer from a top perspective view is between said microlens and said metal bump.

17. The chip package of claim 16, wherein said metal bump further comprises a copper layer and a nickel-containing layer on said copper layer, wherein said tin-containing layer is on said nickel-containing layer.

18. The chip package of claim 16, wherein said spacer comprises a polymer.

19. The chip package of claim 16, wherein said transparent substrate comprises glass.

20. The chip package of claim 16, wherein said nitride layer has a thickness between 0.2 and 0.7 micrometers.