SEMICONDUCTOR UNIT FOR PROTECTING SECONDARY BATTERY, BATTERY PACK HAVING THE SEMICONDUCTOR UNIT BUILT-IN AND ELECTRONIC APPARATUS USING IT

• US 20090121682A1
• Filed: 08/31/2007
• Published: 05/14/2009
• Est. Priority Date: 09/13/2006
• Status: Active Grant

• Current Assignee: Nisshinbo Micro Devices Incorporated (Nisshinbo Holdings Incorporated)
• Original Assignee: Ricoh Company Limited
• Inventors: Goto, Tomoyuki
• Granted Patent: US 7,816,890 B2
• Time in Patent Office: Days
• US Class Current: 320/134
• CPC Class Codes: G01R 31/3648 comprising digital calculation means, e.g. for performing an algorithm
• CPC Class Codes: G01R 31/385 Arrangements for measuring battery or accumulator variables for monitoring G01R31/382
• CPC Class Codes: H01M 10/0525 Rocking-chair batteries, i.e. batteries with lithium insertion or intercalation in both electrodes; Lithium-ion batteries
• CPC Class Codes: H01M 10/425 Structural combination with electronic components, e.g. electronic circuits integrated to the outside of the casing printed circuits H05K1/00
• CPC Class Codes: H01M 10/44 Methods for charging or discharging circuits for charging H02J7/00
• CPC Class Codes: H01M 50/572 Means for preventing undesired use or discharge
• CPC Class Codes: H02J 7/00302 Overcharge protection
• CPC Class Codes: H02J 7/00304 Overcurrent protection
• CPC Class Codes: H02J 7/00306 Overdischarge protection
• CPC Class Codes: Y02E 60/10 Energy storage using batteries

Abstract

A semiconductor unit for protecting a secondary battery has a current detecting terminal converting a charging current to a negative voltage with respect to a negative electrode potential (ground potential) of the secondary battery when the secondary battery is charged, converting the charging current to a positive voltage with respect to the negative electrode potential (ground potential) of the secondary battery when the secondary battery is discharged, and detecting the charging/discharging current; and a test signal generating circuit generating a first test signal when the voltage of the current detecting terminal lowers to a first negative voltage which does not occur in a normal operation state of the semiconductor unit, and generating a second test signal when the voltage of the current detecting terminal lowers to a second negative voltage lower than the first negative voltage.

Claims

1. A semiconductor unit for protecting a secondary battery by detecting overcharge, overdischarge, charging overcurrent, discharging overcurrent or short circuit current, comprising:

a current detecting terminal converting a charging current into a negative voltage with respect to a negative electrode potential (ground potential) of the secondary battery when the secondary battery is charged, converting a discharging current into a positive voltage with respect to the negative electrode potential of the secondary battery when the secondary battery is discharged, and detecting the charging/discharging current; and

a test signal generating circuit generating a first test signal when a voltage of the current detecting terminal is reduced to a first negative voltage which does not occur in a normal operation state of the semiconductor unit, and generating a second test signal when the voltage of the current detecting terminal is reduced to a second negative voltage which is lower than the first negative voltage.

2. The semiconductor unit as claimed in claim 1, further comprising:

a delay circuit delaying output of detecting the overcharge, overdischarge, charging overcurrent, discharging overcurrent or short circuit current;

by a delay time, which is determined for each detecting item, wherein;

either one of the first test signal and the second test signal is used as a signal for shortening the delay time generated by the delay circuit, when the semiconductor unit is tested; and

as a signal for testing the delay circuit, the other one of the first test signal and the second test signal is used.

3. The semiconductor unit as claimed in claim 1, wherein:

the test signal generating circuit at least comprises;

a first inverter circuit of a CMOS configuration in which, for the purpose of generating the first test signal, a negative power supply terminal thereof is connected to the current detecting terminal, and an input terminal thereof is connected to the ground potential or a predetermined potential; and

a second inverter circuit of a CMOS configuration in which, for the purpose of generating the second test signal, a negative power supply terminal thereof is connected to the current detecting terminal, and an input terminal thereof is connected to the ground potential or a predetermined potential.

4. The semiconductor unit as claimed in claim 3, wherein:

an input threshold voltage of the first inverter circuit and an input threshold voltage of the second inverter circuit are different from one another.

5. The semiconductor unit as claimed in claim 4, wherein:

the input threshold voltages of the first and second inverter circuits are set in the different voltage as a result of gate threshold voltages of NMOS transistors having gates connected to the input terminals of the first and second inverter circuits being made different therebetween.

6. The semiconductor unit as claimed in claim 5, wherein:

the gate threshold voltages of the NMOS transistors having the gates connected to the input terminals of the first and second inverter circuits are made different as a result of ratios between gate widths and gate lengths of the NMOS transistors being made different between the first and second inverter circuits.

7. The semiconductor unit as claimed in claim 4, wherein:

the input threshold voltages of the first and second inverter circuits are set in the different voltage as a result of resistors having different resistance values being inserted between sources of NMOS transistors having gates connected to the input terminals of the first and second inverter circuits, and the current detecting terminal.

8. The semiconductor unit as claimed in claim 4, wherein:

the input terminals of the first and second inverter circuits are connected to a common potential.

9. The semiconductor unit as claimed in claim 8, wherein:

the common potential is the ground potential.

10. The semiconductor unit as claimed in claim 3, wherein:

the input terminals of the first and second inverter circuits are connected to different potentials respectively.

11. The semiconductor unit as claimed in claim 3, wherein:

a hysteresis is given to an input threshold voltage of each of the first and second inverter circuits.

12. A battery pack having the semiconductor unit claimed in claim 1 built-in.

13. An electronic apparatus using the battery pack claimed in claim 12.