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CHARACTERIZING CIRCUIT PERFORMANCE BY SEPARATING DEVICE AND INTERCONNECT IMPACT ON SIGNAL DELAY

  • US 20090121737A1
  • Filed: 01/19/2009
  • Published: 05/14/2009
  • Est. Priority Date: 12/18/2003
  • Status: Active Grant
First Claim
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1. A method for analyzing an integrated circuit (IC), the method comprising:

  • creating a first embedded test circuit in the IC for generating a first output delay, the first embedded test circuit comprising a first ring oscillator coupled to a first test load, the first test load being formed in a first interconnect layer of the IC;

    creating a second embedded test circuit in the IC for generating a second output delay, the second embedded test circuit comprising a second ring oscillator, the second ring oscillator being an unloaded ring oscillator, the second ring oscillator being substantially similar to the first ring oscillator;

    providing a first parameter equation and a second parameter equation, the first parameter equation and the second parameter equations specifying a first Front End Of the Line (FEOL) parameter and a first Back End Of the Line (BEOL) parameter, respectively, as functions of the first output delay and the second output delay;

    measuring a first measured output delay and a second measured output delay from the first embedded test circuit and the second embedded test circuit, respectively;

    substituting the first measured output delay and the second measured output delay into the first parameter equation to generate a first FEOL parameter value; and

    substituting the first measured output delay and the second measured output delay into the second parameter equation to generate a first BEOL parameter value.

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