System and method for signal level detection

• US 20090121790A1
• Filed: 11/09/2007
• Published: 05/14/2009
• Est. Priority Date: 11/09/2007
• Status: Active Grant

• Current Assignee: MACOM Connectivity Solutions, LLC (MACOM Technology Solutions Holdings, Inc.)
• Original Assignee: Applied Micro Circuits Corporation (MACOM Technology Solutions Holdings, Inc.)
• Inventors: Blakey, Stan Harry, Brown, Matthew Douglas, Hood, Sheldon James, Fortier, Guy Jacque
• Granted Patent: US 7,698,077 B2
• Time in Patent Office: Days
• US Class Current: 330/279
• CPC Class Codes: G01R 19/04 Measuring peak values or amplitude or envelope of ac or of pulses
• CPC Class Codes: G01R 19/2506 Arrangements for conditioning or analysing measured signals, e.g. for indicating peak values G01R19/003 takes precedence; Details concerning sampling, digitizing or waveform capturing displaying waveforms G01R13/00; analog sampling G01R19/0053
• CPC Class Codes: H03G 3/001 Digital control of analog signals
• CPC Class Codes: H03G 3/3042 in modulators, frequency-changers, transmitters or power amplifiers transmission power control in bidirectional transmission systems H04W52/04
• CPC Class Codes: H03K 5/1532 Peak detectors measuring characteristics of individual pulses G01R29/02
• CPC Class Codes: H03M 3/43 the quantiser being a single bit one
• CPC Class Codes: H03M 3/456 the modulator having a first order loop filter in the feedforward path
• CPC Class Codes: H03M 3/486 by adapting the input gain
• CPC Class Codes: H03M 3/49 in feedback mode, i.e. by determining the range to be selected from one or more previous digital output values

Abstract

An electronic signal level detection system and method are provided. The method receives an analog input signal having a variable voltage and compares the input signal voltage to a threshold. A detection signal is generated for input signal voltages exceeding the threshold in a periodic first time frame. In a second periodic time frame (following the first time frame), a count is updated in response to the generated detection signals. The count is used to create a metric representative of the difference between the input signal voltage and the threshold. The count is incremented in response to the generating a detection signal (“1”) in the first time frame, and decremented in response to not generating a detection signal (“0”) in the first time frame.

Claims

1. An electronic signal level detection method, the method comprising:

receiving an analog input signal having a variable voltage;

comparing the input signal voltage to a threshold;

generating a detection signal for input signal voltages exceeding the threshold in a periodic first time frame;

in response to generating detection signals, updating a count in a periodic second time frame following the first time frame; and

,

using the count to create a metric representation of the difference between the input signal voltage and the threshold.

2. The method of claim 1 wherein updating the count includes:

incrementing the count in response to the generating a detection signal in the first time frame; and

,

decrementing the count in response to not generating a detection signal in the first time frame.

3. The method of claim 2 wherein generating detection signals for input signal voltages exceeding the threshold includes:

in response to detection signals, setting an output of a detection register to a first value; and

,

in response to no detection signals, setting the output of the detection register to a second value, different from the first value.

4. The method of claim 3 wherein comparing the input signal voltage to a threshold includes:

converting the count to an analog offset voltage;

using the offset voltage as the threshold.

5. The method of claim 4 wherein comparing the input signal voltage to a threshold further includes:

summing the input signal voltage with the threshold voltage; and

,

comparing the sum with a fixed comparator input voltage.

6. The method of claim 3 wherein receiving the input signal includes receiving an input signal voltage having a positive voltage with respect to an average input signal voltage, and a variable negative voltage with respect to the average;

wherein comparing the input signal voltage to the threshold includes;

comparing the positive voltage with a high voltage threshold;

comparing the negative voltage with a low voltage threshold;

wherein setting the output of the detection register to the first value in response to detection signals includes;

setting the output of a positive detection register to the first value in response to detection signals in the first time frame; and

,

setting the output of a negative detection register to the first value in response to detection signals in a periodic third time frame following the second time frame;

wherein updating the count includes

updating a positive counter value in the second time frame; and

,

updating a negative counter value in a periodic fourth time frame following the third time frame.

7. The method of claim 6 wherein comparing the input signal voltage to a threshold includes:

converting the positive counter value to a positive offset voltage in the first time frame;

summing the input signal voltage with the positive offset voltage in the first frame; and

,

comparing the sum with a fixed threshold voltage;

converting the negative counter value to a negative offset voltage in the third time frame;

summing the input signal voltage with an inverted negative offset voltage in the third time frame; and

,

comparing the sum to the fixed threshold voltage.

8. The method of claim 7 wherein using the count to create the metric representative of the difference between the input signal voltage and the threshold includes determining an average input signal voltage by summing the positive counter value with the negative counter value.

9. The method of claim 1 further comprising:

determining a loss of signal (LOS) as follows;

in response to reading a count less than a low limit, determining the absence of the input signal; and

,

in response to reading a count greater than a high limit, determining the presence of the input signal.

10. The method of claim 1 wherein using the count to create the predetermined difference between the input signal voltage and the threshold includes:

using the count, adjusting the gain of a variable gain amplifier connected to supply the input signal; and

,

generating the predetermined input signal voltage.

11. The method of claim 3 wherein updating the count includes filtering the count.

12. The method of claim 11 wherein filtering the count includes:

updating an n-bit counter value in response to the detection signals; and

,

supplying the m most significant bits of the counter value to create the predetermined difference between the input signal voltage and the threshold, where m is less than or equal to n.

13. The method of claim 9 wherein determining the LOS includes employing majority decoding with variable parameters of proportion and window size.

14. The method of claim 6 further comprising:

disengaging the input signal voltage;

mitigating common mode offsets in the positive and negative count values in response to disengaging the input voltage signal.

15. An electronic signal level detection system comprising:

a comparison circuit having a first input to receive an analog input signal having a variable voltage, the comparison circuit comparing the input signal voltage to a threshold and supplying a comparator signal at an output for input signal voltages exceeding the threshold;

a detector having an input to receive the comparator signal and an output to supply detection signals responsive to receiving comparator signals in a periodic first time frame;

a counter having an input to receive the detection signals and an output to supply a count in a periodic second time frame following the first time frame; and

,

a digital-to-analog converter (DAC) having an input to receive the count and having an output to supply a threshold voltage, for adjusting the threshold and creating a metric representative of the difference between the input signal voltage and the threshold in response to the count.

16. The system of claim 15 wherein the counter increments the count in response to receiving a detection signal in the first time frame, and decrements the count in response to not receiving a detection signal in the first time frame.

17. The system of claim 16 wherein the detector is a detection register setting a detection register output to a first value in response to receiving a comparator signal, and setting the detection register output to a second value, different from the first value, in response to not receiving a comparator signal.

18. The system of claim 17 wherein the comparison circuit includes:

a summing circuit having an input to accept the input signal voltage, an input connected to accept the threshold voltage, and an output to supply a sum voltage; and

,

a comparator having a first input to accept the sum voltage, a second input connected to a fixed comparator input voltage, and an output to supply the comparator signal.

19. The system of claim 17 wherein the comparison circuit is a comparator having a first input to accept the input signal voltage, a second input to accept the threshold voltage, and an output to supply the comparator signal.

20. The system of claim 18 wherein the comparator compares an input signal voltage having a positive voltage with respect to an average input signal voltage, to a high voltage threshold in the first time frame, and compares a variable negative voltage with respect to the average, to the low voltage threshold in a periodic third time frame following the second time frame;

wherein the detection register sets a positive detection register output to the first value in response to receiving comparator signals in the first time frame, and sets a negative detection register output to the first value in response to receiving comparator signals in the third time frame; and

,

wherein the counter supplies a positive counter value in the second time frame and supplies a negative counter value in a periodic fourth time frame following the third time frame.

21. The system of claim 20 wherein the DAC converts the positive counter value to a positive offset voltage in the first time frame, converts the negative counter value to a negative offset voltage in the third time frame, and supplies an inverted negative offset voltage;

and,

wherein the summing circuit sums the input signal voltage with the positive offset voltage in the first frame, and sums the input signal voltage with the inverted negative offset voltage in the third time frame.

22. The system of claim 21 further comprising:

an averaging circuit having inputs to accept the positive and negative counter values, and supplying an average input signal voltage measurement at an output, determined by summing the positive counter value with the negative counter value.

23. The system of claim 15 further comprising:

a loss-of-signal circuit having an input connected to the counter to accept the count, and having an output to supply a message indicating the absence of the input signal in response to reading a count less than a low limit, and a message determining the presence of the input signal in response to reading a count greater than a high limit.

24. The system of claim 15 further comprising:

a variable gain amplifier having an input to accept a signal, a control input connected to receive the count, and an output to the comparison circuit to supply the input signal voltage, the amplifier adjusting the gain in response to the count.

25. The system of claim 15 wherein the counter supplies an n-bit counter value in response to the detection signals;

and,

wherein the DAC accepts the m most significant bits of the counter value, where m is less than or equal to n.