High Frequency Digital Oscillator-on-Demand with Synchronization

• US 20090121797A1
• Filed: 01/20/2009
• Published: 05/14/2009
• Est. Priority Date: 08/22/2007
• Status: Active Grant

• Current Assignee: Urenschi Assets Limited Liability Company (Intellectual Ventures LLC)
• Original Assignee: Chris Karabatsos
• Inventors: Karabatsos, Chris
• Granted Patent: US 7,605,666 B2
• Time in Patent Office: Days
• US Class Current: 331/57
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: H03K 2005/00058 controlled by a digital setting
• CPC Class Codes: H03K 2005/00071 by adding capacitance as a load
• CPC Class Codes: H03K 23/502 with a base or a radix other than a power of two H03K23/54 takes precedence
• CPC Class Codes: H03K 23/54 Ring counters, i.e. feedback shift register counters H03K23/52 takes precedence
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03K 5/133 using a chain of active delay devices

Abstract

A High Frequency Digital Oscillator contains a ring oscillator having an output fn, and having coarse and fine frequency adjustments, wherein the input signal f1 is the input to both the ring oscillator and the High-Frequency Digital Oscillator, which has a multiplicity of output signals including f2, f4, and f8 at one-half, one fourth, and one-eighth the frequency of fn respectively, and wherein an input gating signal causes the oscillator to start or stop, a signal fc=¼*(f4) causing a coarse frequency adjustment and a signal Δ=(1/f1−1/fc) making a fine adjustment, and by stopping the new output before the rising edge of f1; and then restarting starting the new output at the rising edge of so that the output and input are synchronized.

Claims

1. A method to produce a digital on-demand digital oscillator of high frequency and to derive lower frequency clocks by digital division, and having the ability to start and stop oscillating, almost instantaneously, and remaining synchronized to an external clock, the method comprising the steps of:

a) incorporating a base oscillator comprising a feedback loop, wherein the feedback loop comprises both a bulk delay and a fine delay, and wherein said base oscillator is designed to oscillate at a nominal frequency fn which is 2ⁿ times that of the external clock fclk, with n being a integer;

b) calculating the number nb of periods of the base oscillator which are equal or less than the period nclk of the external clock;

c) setting the bulk delay delta B equal to nb*pn, where pn=1/fn;

d) setting the fine delay delta F equal to pclk−

delta B where pclk=1/fclk,

so that after including the bulk and fine delays in the feedback loop the base oscillator will have a frequency of 2ⁿ times the external clock,

and the method further comprising the steps of;

e) gating the on-demand oscillator to an “

ON”

state in synchronization with the external clock, in order to begin oscillating,

wherein steps b) through e) are performed within one period of the external clock, and wherein phase locked loops are not used in the on-demand oscillator.

2. The method of claim 1, further comprising the step of incorporating a multiplicity of frequency dividers and phase shifters to the output of the base oscillator, so that signals with frequencies of 2*fclk, 4*fclk, etc. up to 2ⁿ*fclk, all synchronized with the external clock, are generated.

3. The method of claim 2, wherein the calculating the number nb of periods of the base oscillator which are equal or less than the period nclk of the external clock is performed by a digital comparator.

4. The method of claim 3, wherein the setting the fine delay delta F is performed by a plurality of digital delay circuits.

5. The method of claim 3, wherein setting of the bulk delay delta B and setting of the fine delay delta F further comprises incorporating multiple delay paths in the feedback loop.

6. The method of claim 3, wherein setting of the bulk delay delta B and setting of the fine delay delta F further comprises incorporating a multiplicity of passive circuits in the feedback loop.

7. The method of claim 3, wherein setting of the bulk delay delta B and setting of the fine delay delta F further comprises self-regulating of temperature, voltage and process variation.

8. The method of claim 3, further comprising repeatedly setting of the bulk delay delta B and of the fine delay delta F, to correct variations due to heat and voltage changes.

9. The method of claim 3, further comprising incorporating additional feedback loops in the on-demand oscillator, and further comprising bypassing or selecting each one or more of said additional loops and for inserting the measured bulk and fine delays into one or more of said additional loops.

10. An electronic digital on-demand digital oscillator system of high frequency which produces lower frequency clocks by digital division, and which has the ability to start and stop oscillating, almost instantaneously, while remaining synchronized to an external clock, said system comprising:

a) a base oscillator comprising a feedback loop, wherein the feedback loop comprises both a bulk delay and a fine delay, and wherein said base oscillator is designed to oscillate at a nominal frequency fn which is 2ⁿ times that of the external clock fclk, with n being a integer;

b) means for calculating the number nb of periods of the base oscillator which are equal of less than the period nclk of the external clock;

c) means for setting the bulk delay delta B equal to nb*pn, where pn=1/fn;

d) means for setting the fine delay delta F equal to pclk−

delta B where pclk=1/fclk,

so that after including the bulk and fine delays in the feedback loop the base oscillator will have a frequency of 2ⁿ times the external clock, and the system further comprising;

e) gating means to set the on-demand oscillator to an “

ON”

state in synchronization with the external clock, on to begin oscillating,

wherein phase locked loops are not used in the on-demand oscillator system.

11. The system of claim 10, wherein a multiplicity of frequency dividers and phase shifters are electronically affixed to the output of the base oscillator, so that signals with frequencies of 2*fclk, 4*fclk, etc. up to 2ⁿ*fclk are generated.

12. The system of claim 11, further comprising a digital comparator which comprises the calculating of the number nb of periods of the base oscillator which are equal or less than the period nclk of the external clock.

13. The system of claim 12, further comprising a plurality of digital delay circuits which comprise the setting the fine delay delta F.

14. The system of claim 12, further comprising a multiplicity of delay paths in the feedback loop which comprise the setting of the bulk delay delta B and setting of the fine delay delta F.

15. The method of claim 12, further comprising a multiplicity of passive circuits in the feedback loop which comprise the setting of the bulk delay delta B and setting of the fine delay delta F.

16. The system of claim 12, further comprising means for self regulation of temperature, voltage and process variation which comprise the setting of the bulk delay delta B and setting of the fine delay delta F

17. The system of claim 12, further comprising means for repeatedly setting of the bulk delay delta B and for setting of the fine delay delta F in order to correct variations due to heat and voltage changes.

18. The system of claim 12, further comprising one or more additional feedback loops in the on-demand oscillator, and further comprising means for bypassing and means of selecting one or more of said additional loops and means for inserting the measured delays into one or more of said additional loops.