METHOD OF MAKING INTEGRATED CIRCUIT EMBEDDED WITH NON-VOLATILE PROGRAMMABLE MEMORY HAVING VARIABLE COUPLING

• US 20090124054A1
• Filed: 11/14/2008
• Published: 05/14/2009
• Est. Priority Date: 11/14/2007
• Status: Active Grant

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Original Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Inventors: Gross, John Nicholas, Liu, David K.Y.
• Granted Patent: US 8,580,622 B2
• Time in Patent Office: Days
• US Class Current: 438/257
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/60 the control gate being a doped region, e.g. single-poly memory cell
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A programmable non-volatile device is made with a floating gate that functions as a FET gate that overlaps a portion of a source/drain region and allows for variable coupling through geometry and/or biasing conditions. This allows a programming voltage for the device to be imparted to the floating gate through variable capacitive coupling, thus changing the state of the device. Multi-state embodiments are also possible. The invention can be used in environments such as data encryption, reference trimming, manufacturing ID, security ID, and many other applications.

Claims

1. A method of forming a non-volatile programmable memory device situated on a substrate comprising:

forming a gate for non-volatile programmable memory device from a first layer;

wherein said first layer is shared by the non-volatile programmable memory device and at least one other device also situated on the substrate and associated with a logic gate and/or a volatile memory;

forming a drain region comprised of a first drain region and at least one separate second drain region; and

varying an amount of capacitive coupling between said gate said drain region by selectively overlapping portions of said gate with both said first drain region and said at least one second drain.

2. The method of claim 1 wherein said first layer is polysilicon.

3. The method of claim 1 wherein said first layer is an insulating layer.

4. The method of claim 3 wherein said gate further includes impurities, which impurities are introduced during a source or drain implant step.

5. The method of claim 1 wherein said device is formed with n-type channel.

6. The method of claim 1 wherein said non-volatile programmable memory device is embedded in a computing circuit and formed entirely by masks used to form other logic and/or memory n-channel devices in said processing circuit.

7. The method of claim 6 wherein said non-volatile programmable memory device is embedded in a computing circuit and formed entirely by CMOS processing steps used to form other logic and/or memory devices in said computing circuit.

8. The method of claim 1 wherein said non-volatile programmable memory device is associated with one of the following:

a data encryption circuit;

a reference trimming circuit;

a manufacturing ID; and

/or a security ID.

9. The method of claim 1, wherein said capacitive coupling takes place in a first trench situated in the substrate.

10. The method of claim 9 wherein a set of second trenches in said substrate are used as embedded DRAM.

11. The method of claim 1 further including a step:

forming a second programmable device coupled in a paired latch arrangement such a datum and its compliment can be stored in said paired latch.

12. The method of claim 1 wherein said non-volatile programmable memory device can only be programmed once.

13. The method of claim 1 wherein said non-volatile programmable memory device can be erased and re-programmed.

14. The method of claim 1 wherein said non-volatile programmable memory device is used to store an identification code for a wafer.

15. The method of claim 1 further including a step:

programming said non-volatile programmable memory device during manufacture of a wafer to store an identification code.

16. The method of claim 15 further including a step:

programming a second non-volatile programmable memory device during manufacture of the wafer to store a second identification code.

17. The method of claim 1 wherein said non-volatile programmable memory device has a non-conducting channel at a completion of manufacturing of such device.

18. The method of claim 1 wherein said non-volatile programmable memory device is part of an array.

19. The method of claim 1, wherein the device is adapted to be read by a bias voltage applied to one of said first drain region and/or said at least one separate second drain region which is adjusted with time to determine a threshold voltage of said floating gate.

20. The method of claim 1 wherein the non-volatile memory device is adapted so that more than one bit of information can be stored in response to a programming voltage.

21. A method of forming a one-time programmable (OTP) memory device incorporated on a silicon substrate with one or more other additional logic and/or non-OTP memory devices, characterized in that:

a. said OTP memory device has a drain region capacitively coupled to a floating gate; and

b. any and all regions and structures of said OTP memory device are formed in common with corresponding regions and structures used as components of the additional logic and/or non-OTP memory devices;

c. an amount of capacitive coupling between said floating gate and said drain region can be varied during different program, erase and/or read operations by varying an amount of overlap between said drain region and said floating gate.

22. A method of forming a multi-level one-time programmable (MOTP) memory cell incorporated on a silicon substrate with one or more other additional logic and/or non-MOTP memory devices, characterized in that:

a. said MOTP memory cell has a drain region capacitively coupled to a floating gate; and

b. any and all regions and structures of said MOTP memory cell are formed in common with corresponding regions and structures used as components of the additional logic and/or non-MOTP memory devices;

c. an amount of capacitive coupling between said floating gate and said drain region can be varied during a program operation to store multiple bits of data within a single MOTP memory cell.