Method of Providing Electrical Separation in Integrated Devices and Related Devices

• US 20090124058A1
• Filed: 01/21/2009
• Published: 05/14/2009
• Est. Priority Date: 08/15/2005
• Status: Active Grant

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies Wireless IP Pte Limited
• Inventors: Rigo, Cesare, Vallone, Marco, Agresti, Michele
• Granted Patent: US 7,867,792 B2
• Time in Patent Office: Days
• US Class Current: 438/403
• CPC Class Codes: H01S 5/026 Monolithically integrated components, e.g. waveguides, monitoring photo-detectors, drivers stabilisation of output H01S5/06
• CPC Class Codes: H01S 5/0265 Intensity modulators intra-cavity modulators H01S5/0625
• CPC Class Codes: H01S 5/042 Electrical excitation ; Circuits therefor monolithically integrated laser drive components H01S5/0261

Abstract

An integrated device includes two sections (A, B), such as a DFB laser (A) and an EAM modulator (B), having a semi-insulating (SI) separation region therebetween. The separation region (24) is of a material acting as a trap on electrons and configured to impede current flow between the two sections (A, B) due to holes. The separation region (24) may be of a material acting as a trap both on electrons and holes. Alternatively, the separation region (24) is of a material that acts as a trap on electrons and is provided over a p-type substrate (20) common to the two sections (A, B).

Claims

1. A method of providing a semi-insulating (SI) separation region between two sections A and B of an integrated device, the method comprising making said separation region of a material acting as a trap for electrons and to impede current flow between sections A and B due to holes, the material of the separation region comprising AlGaInAs.

2. The method of claim 1, further comprising configuring the material to act as a trap for electrons and holes.

3. The method of claim 1, further comprising:

configuring the material to act as a trap for electrons;

providing a p-type substrate common to sections A and B, and

forming the separation region over the p-type substrate common to sections A and B.

4. The method of claim 3, further comprising providing the separation region with a reversed structure starting from the p-type substrate and having an upper n-type cladding disposed over the A and B sections.

5. The method of claim 1, further comprising configuring the material have deep acceptor levels acting as an electron trap.

6. The method of claim 1, further comprising including an iron-doped material in the separation region.

7. The method of claim 1, further comprising including InGaAsP in the separation region.

8. The method of claim 1, further comprising configuring the material to have deep level traps acting on both electrons and holes.

10. The method of claim 1, further comprising:

etching a transition region between sections A and B, and

depositing the material in the transition region to form the semi-insulating separation region.

11. The method of claim 1, further comprising butt-coupling sections the semi-insulating separation region to sections A and B.

12. The method of claim 1, further comprising providing one of sections A and B as a laser source.

13. The method of claim 12, further comprising configuring the laser source as a distributed feedback laser source.

14. The method of claim 13, further comprising forming a DFB grating over one of sections A and B.

15. The method of claim 1, further comprising configuring one of sections A and B as a modulator.

16. The method of claim 15, further comprising configuring one of sections A and B as an EAM modulator.

9. (canceled)

17. (canceled)

18. (canceled)

19. (canceled)

20. (canceled)

21. (canceled)

22. (canceled)

23. (canceled)

24. (canceled)

25. (canceled)

26. (canceled)

27. (canceled)

28. (canceled)

29. (canceled)

30. (canceled)

31. (canceled)

32. (canceled)

33. (canceled)

34. (canceled)