Asymmetrical IO Method and System

• US 20090125747A1
• Filed: 01/21/2009
• Published: 05/14/2009
• Est. Priority Date: 09/19/2005
• Status: Active Grant

• Current Assignee: ATI Technologies Incorporated (Advanced Micro Devices, Inc.)
• Original Assignee: ATI Technologies Incorporated (Advanced Micro Devices, Inc.)
• Inventors: Lee, Ming-Ju E., Morein, Stephen, Chen, Lin, Macri, Joseph, Gauthier, Claude
• Granted Patent: US 8,301,930 B2
• Time in Patent Office: Days
• US Class Current: 713/400
• CPC Class Codes: H04L 7/0025 interpolation of clock signal
• CPC Class Codes: H04L 7/0091 Transmitter details
• CPC Class Codes: H04L 7/02 Speed or phase control by the received code signals, the signals containing no special synchronisation information H04L7/0075 takes precedence

Abstract

An asymmetrical IO method and system are described. In one embodiment, a host device includes shared resources for data synchronization of the host device and a client device. The shared resources include a shared phase interpolator. In an embodiment, data lines between the host and client are also used to transmit phase information from the client device to the host device, obviating the need for additional, dedicated lines or pins.

Claims

1. A system, comprising:

a client device configured to transmit data to a host device, receive data from a host device, and transmit client clock phase information to the host device during an electrical turnaround time between read and write operations over a data bus coupling the client device and the host device; and

a host device configured to receive the client clock phase information from the client device, the host device comprising shared data synchronization resources that use the client clock phase information to adjust a host clock for transmitting data to the at least one client device, wherein the shared resources are shared between transmit and receive functions of the host device.

2-20. -20. (canceled)