Method for controlling a DRAM

• US 20090125761A1
• Filed: 05/07/2008
• Published: 05/14/2009
• Est. Priority Date: 11/14/2007
• Status: Abandoned Application

• Current Assignee: Etron Technology Inc
• Original Assignee: Etron Technology Inc
• Inventors: Hung, Bin-Feng, Huang, Ming-Sung, Lu, Wen-Min
• Application Number:
  US12/116,208
• Publication Number:
  US 20090125761A1
• Time in Patent Office: Days
• US Class Current: 714/718
• CPC Class Codes: G11C 29/70 Masking faults in memories by using spares or by reconfiguring

Abstract

A method for controlling a DRAM includes detecting failed memory cells of the DRAM, recording the rows corresponding to the failed memory cells, receiving a control signal for accessing the memory cell with column address X and row address Y, determining if the row address Y is in the recorded failed rows list, and if yes, replacing the memory cell to be accessed with the memory cell with the column address X and row address Z which is not same as Y.

Claims

1. A method for controlling a DRAM, the DRAM comprising a memory array constructed by memory cells of M columns and N rows, the method comprising:

detecting defect memory cells of the DRAM;

recording corresponding rows of the detected defect memory cells;

receiving a control command for accessing a memory cell located in an X column and a Y row of the DRAM;

detecting if the Y row is in the recorded rows of the detected defect memory cells; and

accessing a memory cell located in the X column and a Z row of the DRAM according to the control command and the detecting result.

2. The method of claim 1 further comprising setting at least one row of memory cells as reserved row memory cells.

3. The method of claim 2 wherein accessing a memory cell located in the X column and the Z row of the DRAM according to the control command and the detecting result comprises when the Y row is not in the recorded rows of the detected defect memory cells, accessing the memory cell located in the X column and the Y row of the DRAM according to the control command.

4. The method of claim 2 wherein accessing a memory cell located in the X column and the Z row of the DRAM according to the control command and the detecting result comprises when the Y row is in the recorded rows of the detected defect memory cells, accessing the memory cell located in the X column and the Z row of the DRAM according to the control command and Z is not equal to Y.

5. The method of claim 4 wherein the memory cells of the Z row is included in the reserved row memory cells.

6. The method of claim 2 wherein setting at least one row of memory cells as reserved row memory cells comprises setting at least one row of memory cells as reserved row memory cells according to the recorded rows of the detected defect memory cells for ensuring the reserved row memory cells from being defect.

7. The method of claim 2 wherein setting at least one row of memory cells as reserved row memory cells comprises setting at least one row of memory cells with lower possibility of being used as reserved row memory cells.

8. The method of claim 2 wherein setting at least one row of memory cells as reserved row memory cells comprises setting number of rows of memory cells as reserved row memory cells according to number of the recorded rows of the detected defect memory cells.