MEMORY SYSTEM AND RELATED METHOD USING SOFTWARE-DEFINED RADIO WITH WRITE-PROTECTED, NON-VOLATILE MEMORY

• US 20090125782A1
• Filed: 11/12/2007
• Published: 05/14/2009
• Est. Priority Date: 11/12/2007
• Status: Active Grant

• Current Assignee: Harris Global Communications, Inc. (L3Harris Technologies, Inc.)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Carlson, David F., JOSEFIAK, Brent, Dragon, Glen
• Granted Patent: US 8,074,145 B2
• Time in Patent Office: Days
• US Class Current: 714/758
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7211 Wear leveling

Abstract

A software-defined radio includes a radio circuit and an executable radio software system operable with the radio circuit and conforming to the software communications architecture (SCA) specification and defining an operating environment that allows a waveform application to operate with the radio circuit for transmitting and receiving voice and data. A write-protected non-volatile memory is operable with the radio circuit and executable radio software system and has a write enable controlled by a non-driver program such that a wear leveling correction sequence is deferred.

Claims

1. A software-defined radio, comprising:

a radio circuit;

an executable radio software system operable with the radio circuit and conforming to the Software Communications Architecture (SCA) specification and defining an operating environment that allows a waveform application to operate with the radio circuit for transmitting and receiving voice and data; and

a write protected non-volatile memory operable with the radio circuit and executable radio software system and having a write enable controlled by a non-driver program such that a wear leveling correction sequence is deferred.

2. The software-defined radio according to claim 1, wherein said write protected non-volatile memory comprises a NAND memory.

3. The software-defined radio according to claim 1, wherein said write protected non-volatile memory includes a write enable pin that is disabled by a third party outside the control of a driver used normally for wear leveling correction sequences.

4. The software-defined radio according to claim 1, wherein said radio circuit is operable as an internet protocol (IP) data radio.

5. The software-defined radio according to claim 1, and further comprising a RAM, a driver, and a file system for reading transaction requests on pages in blocks, wherein said file system and driver retrieve a block as a suspect block upon detection of an Error Correction Code (ECC) after a page read and copy the suspect block into RAM for fulfilling file requests.

6. The software-defined radio according to claim 5, and further comprising a writeable non-volatile memory into which the suspect block is copied and later replaced after entering a write enabled mode.

7. The software-defined radio according to claim 6, and further comprising an integrity assurance program that erases the suspect block and replaces any erased data within the write protected non-volatile memory from data within the writeable non-volatile memory.

8. The software-defined radio according to claim 5, wherein an ECC correction triggers a copyout routine.

9. The software-defined radio according to claim 1, wherein said file system is operable for providing a cyclic redundancy check (CRC) error detection.

10. A method for controlling memory within a software-defined radio that includes a radio circuit and an executable radio software system operable with the radio circuit and conforming to the Software Communications Architecture (SCA) specification and defining an operating environment that allows a waveform application to operate with the radio circuit for transmitting and receiving voice and data, comprising:

returning an error correction code (ECC) after reading the memory; and

deferring a wear leveling correction on the memory.

11. The method according to claim 10, which further comprises disabling a write enable pin normally used for wear leveling correction such that the write enable pin is controlled by a third party outside the control of a driver normally used in controlling the wear leveling correction.

12. The method according to claim 11, which further comprises reading transaction requests on pages in blocks and retrieving a block as a suspect block upon detection of an Error Correction Code (ECC) after a page read and copying the suspect block into RAM for fulfilling file requests.

13. The method according to claim 12, which further comprises replacing the suspect block after entering a write enabled mode.

14. The method according to claim 12, which further comprises replacing any erased data within a write protected non-volatile memory from data in the writeable non-volatile memory.

15. The method according to claim 12, which further comprises triggering a copyout routine after an ECC correction.

16. The method according to claim 10, which further comprises providing a cyclic redundancy check (CRC) error detection.

17. The method according to claim 10, wherein the memory comprises a NAND memory.

18. The method according to claim 10, which further comprises operating the radio circuit as an internet protocol (IP) data radio.

19. A memory system, comprising:

a write protected, non-volatile memory having a write enable controlled by a non-driver third party program outside the control of any driver used normally for wear leveling correction sequences;

a RAM;

a driver; and

a file system wherein the file system and driver are operative for retrieving a block as a suspect block upon detection of an Error Correction Code (ECC) after a page read and copying the suspect block into RAM for fulfilling file requests while deferring a wear leveling correction sequence.

20. The memory system according to claim 19, wherein said write protected non-volatile memory comprises a NAND memory.

21. The memory system according to claim 19, and further comprising a writeable nonvolatile memory into which the suspect block is copied and later replaced after entering a write enabled mode.

22. The memory system according to claim 21, and further comprising an integrity assurance program that erases the suspect block and replaces any erased data within the write protected non-volatile memory from data within the writeable non-volatile memory.

23. The memory system according to claim 21, wherein an ECC correction triggers a copyout routine.

24. The memory system according to claim 19, wherein said file system is operable for providing a cyclic redundancy check (CRC) error detection.