Pipelined Data Relocation and Improved Chip Architectures
First Claim
1. A memory system, comprising:
- a controller; and
a memory, includinga non-volatile data storage section;
a first data register connectable to the non-volatile data storage section to transfer data between the first data register and the non-volatile data storage section; and
a second data register, connectable to the controller to transfer data between the second data register and the controller, wherein the memory exchanges the contents of the first data register with the contents of the second data register in response to a command from the controller.
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Accused Products
Abstract
The present invention present methods and architectures for the pipelining of read operation with write operations. In particular, methods are presented for pipelining data relocation operations that allow for the checking and correction of data in the controller prior to its being re-written, but diminish or eliminate the additional time penalty this would normally incur. A number of architectural improve are described to facilitate these methods, including: introducing two registers on the memory where each is independently accessible by the controller; allowing a first memory register to be written from while a second register is written to; introducing two registers on the memory where the contents of the registers can be swapped.
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Citations
30 Claims
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1. A memory system, comprising:
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a controller; and a memory, including a non-volatile data storage section; a first data register connectable to the non-volatile data storage section to transfer data between the first data register and the non-volatile data storage section; and a second data register, connectable to the controller to transfer data between the second data register and the controller, wherein the memory exchanges the contents of the first data register with the contents of the second data register in response to a command from the controller. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A memory system, comprising:
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a controller including a plurality of data buffers; and a memory including a non-volatile data storage section and one or more data registers, wherein the controller can perform a data checking operation on the contents of a first of said data buffers while concurrently transferring data between another of said data buffers and one of said data registers. - View Dependent Claims (12, 13, 14, 15)
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16. A method of operating a memory system comprising a controller and a memory including first and second data registers and a non-volatile data storage section, the method comprising:
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loading first data into a first of said data registers from either the data storage section or the controller; loading second data into the second of said data registers from either the data storage section or the controller; and swapping the memory the contents of the first and second data registers in response to a command from the controller. - View Dependent Claims (17, 18, 19)
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20. A method of operating a memory system comprising a controller including first and second data buffers and a memory including a non-volatile data storage section, the method comprising:
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performing a data checking operation on first data stored in a first of the data buffers; and concurrently transferring second data between the second of the of the data buffers and the memory. - View Dependent Claims (21, 22)
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23. A method of operating a memory system comprising a controller and a memory including one or more data registers and a non-volatile data storage section, the method comprising sequentially performing in a pipelined manner a plurality of program operations, each of said program operations sequentially comprising the sub-operations of:
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writing a data set from one of said one or more data registers to the non-volatile data storage section; reading the data set as written back to one of said one or more data registers; transferring the data set as written back to the controller; and verifying by the controller of the set data as written, wherein the verifying of the data set for one programming operation is performed concurrently with the writing sub-operation of the following programming operation. - View Dependent Claims (24)
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25. A method of operating a memory system comprising a controller and a memory a plurality of memory chips, each including one or more data registers and a non-volatile data storage section, the method comprising sequentially performing in a pipelined manner a plurality of data relocation operations on two or more of said memory chips, each of said data relocation operations on a given one of the memory chips sequentially comprising the sub-operations of:
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reading a data set from the storage section to one of said one or more data registers; transferring the data set to the controller; checking/correcting the data set, wherein said checking/correcting the data set includes; determining the quality of the data set; and if the quality of the data set is not acceptable, correcting the data set; if the data set is corrected, transferring the corrected data set back to one of said one or more data registers; and programming the data back to the storage section, wherein the checking/correcting of a first data set for one data relocation operation in a first memory chip is performed concurrently with a sub-operation of a second data set for the following data relocation operation in the first memory chip and concurrently with a sub-operation of a first data set for the following data relocation operation in a second memory chip. - View Dependent Claims (26, 27, 28, 29, 30)
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Specification