Hardware based memory scrubbing

• US 20090125788A1
• Filed: 01/05/2009
• Published: 05/14/2009
• Est. Priority Date: 03/16/2005
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: Andrew Ray Wheeler, James Richard Peterson
• Inventors: Peterson, James R., Wheeler, Andrew Ray
• Granted Patent: US 8,307,259 B2
• Time in Patent Office: Days
• US Class Current: 714/764
• CPC Class Codes: G06F 11/106 Correcting systematically all correctable errors, i.e. scrubbing
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

This application relates to hardware based memory scrubbing. One disclosed embodiment may comprise a system that includes an engine, implemented in hardware, configured to initiate a request for data residing in associated memory. An error system is configured to detect errors in data that has been read from associated memory in response to the request for the data, the error system maintaining a log of entries corresponding to errors detected by the error system. An identifier is associated with each of the entries in the log that result from the request initiated by the engine to differentiate from other entries in the log.

Claims

1. A system comprising:

an engine, implemented in hardware, configured to initiate a request for data residing in associated memory; and

an error system configured to detect errors in data that has been read from the associated memory in response to the request for the data, the error system maintaining a log of entries corresponding to errors detected by the error system, an identifier being associated with each of the entries in the log that result from the request initiated by the engine to differentiate from other entries in the log.

2. The system of claim 1, wherein the engine is configured to correct a correctable error in the associated memory based on the error system detecting and correcting the correctable error in response to the request initiated by the engine.

3. The system of claim 1, wherein the engine further comprises:

a mode register having a value that defines an operating mode for the engine; and

a memory range register that defines a range of memory addresses in the associated memory, the engine initiating requests for data in the associated memory according to the range of memory addresses in the memory range register.

4. The system of claim 3, wherein the engine is configured to operate in at least two modes, a first mode corresponding to a test and initialization mode and a second mode corresponding to a proactive scrubbing mode.

5. The system of claim 4, wherein the engine further comprises test and initialization circuitry employed during the first mode to test and initialize the associated memory based on the range of memory addresses in the memory range register.

6. The system of claim 5, wherein the system further comprises a pseudorandom number generator that is controlled by the test and initialization circuitry to generate at least one pseudorandom value, the engine causing the at least one pseudorandom value to be written to and read from the associated memory so that the error system can detect errors in the associated memory based on the range of memory addresses being tested during the first mode.

7. The system of claim 3, further comprising firmware that controls the engine by setting the value in the mode register and by setting the range of memory addresses in the memory range register.

8. The system of claim 7, wherein the error system is configured to detect a type of error for data that has been read from the associated memory in response to the request initiated by the engine, the firmware further comprising error handling control that can differentiate between an error resulting from the request initiated by the engine and an error resulting from a request initiated by another requestor based on the agent identifier in the request initiated by the engine.

9. The system of claim 8, wherein the error handling control further comprises a deallocation engine that can selectively modify a data structure to deallocate portions of the associated memory from use in a computer system based at least in part on information in the log.

10. The system of claim 1, wherein the engine and the error system form at least a portion of an input/output controller that is operably coupled with the associated memory and with at least one processor, the engine being a direct memory access engine operating in a coherency domain of the at least one processor, such that the request initiated by the engine can be provided to access the associated memory and to cache of the at least one processor.

11. The system of claim 1, further comprising firmware that controls the engine to test and initialize at least a portion of the associated memory during a first operating mode, the firmware controlling the engine to proactively scrub the associated memory during a second operating mode by initiating the request for data residing in at least a portion of the associated memory.

12. The system of claim 11, wherein the firmware implements error handling control that can vary during the second operating mode based on the agent identifier associated with the entries in the log, the agent identifier enabling the firmware to differentiate between errors resulting from the requests initiated by the engine and an error resulting from a request initiated by another requestor.

13. The system of claim 1, wherein the log further comprises a data structure for each of the entries in the log, the data structure for each of the entries comprising:

a first field that identifies a given agent that initiated a given request that resulted in a corresponding error being entered into the log; and

at least one second field that identifies a type of the corresponding error.

31. The system of claim 1 where the error system selectively modifies a data structure based on the log of entries.

32. The system of claim 1 where the engine is configured to initiate the request for data to identify and proactively scrub error data from the associated memory according to a scrub cycle, where the scrub cycle limits an amount of time that errors remain in the associated memory.

33. The system of claim 32, where the engine is configured to scrub the associated memory by:

reading and testing data from a location in the associated memory to identify errors;

storing an entry in the log of entries for an identified error and assigning an identifier to uniquely identify errors resulting from the testing initiated by the scrub engine; and

scrubbing memory locations in the associated memory that are identified as being identified from the testing initiated by the engine.

35. The method of claim 32 comprising:

selectively modifying a data structure based on the log of entries.

36. The method of claim 32 where the initiating a request is a memory scrubbing request initiated in accordance with a scrub interval.

14-30. -30. (canceled)

34. A computer implemented method comprising:

initiating a request to read data residing in an associated memory;

detecting errors in the data that has been read from the associated memory in response to the request;

storing and maintaining a log of entries corresponding to errors detected;

generating and storing an identifier associated with each of the entries in the log that result from the request to read data to differentiate from other entries in the log.