Thin film field effect transistor and display using the same

• US 20090127550A1
• Filed: 11/12/2008
• Published: 05/21/2009
• Est. Priority Date: 11/15/2007
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Fujifilm Corporation (Fujifilm Holdings Corporation)
• Inventors: Imai, Shinji
• Granted Patent: US 7,982,216 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A TFT is provided which includes, on a substrate, at least a gate electrode, a gate insulating layer; an active layer containing an amorphous oxide semiconductor, a source electrode, and a drain electrode, wherein a carrier concentration of the active layer is 3×10¹⁷ cm⁻³ or more and a film thickness of the active layer is 0.5 nm or more and less than 10 nm. A TFT is provided which has a low OFF current and a high ON-OFF ratio, and is improved in environmental temperature dependency. Also, a display using the TFT is provided.

Claims

1. A thin film field effect transistor comprising, on a substrate, at least a gate electrode, a gate insulating layer, an active layer containing an amorphous oxide semiconductor, a source electrode, and a drain electrode;

wherein a carrier concentration of the active layer is 3×

10¹⁷ cm<sup>−

3</sup> or more, and a film thickness of the active layer is 0.5 nm or more and less than 10 nm.

2. The thin film field effect transistor according to claim 1, wherein the active layer contains at least one selected from the group consisting of In, Ga, Zn and Sn.

3. The thin film field effect transistor according to claim 2, wherein the active layer contains In and Zn.

4. The thin film field effect transistor according to claim 1, further comprising a low carrier concentration layer that is in contact with the active layer on the opposite side of the active layer from the gate insulating layer and has a carrier concentration of 10¹⁶ cm⁻

3 or less.

5. The thin film field effect transistor according to claim 2, further comprising a low carrier concentration layer that is in contact with the active layer on the opposite side of the active layer from the gate insulating layer and has a carrier concentration of 10¹⁶ cm⁻

3 or less.

6. The thin film field effect transistor according to claim 3, further comprising a low carrier concentration layer that is in contact with the active layer on the opposite side of the active layer from the gate insulating layer and has a carrier concentration of 10¹⁶ cm⁻

3 or less.

7. The thin film field effect transistor according to claim 4, wherein the low carrier concentration layer is an amorphous oxide semiconductor layer.

8. The thin film field effect transistor according to claim 7, wherein the amorphous oxide semiconductor in the low carrier concentration layer contains at least one selected from the group consisting of In, Ga, Zn and Sn.

9. The thin film field effect transistor according to claim 8, wherein the amorphous oxide semiconductor in the low carrier concentration layer contains In and Zn.

10. The thin film field effect transistor according to claim 1, wherein a roughness of an interface between the gate insulating layer and the active layer is less than 2 nm.

11. The thin film field effect transistor according to claim 1, wherein the substrate is a flexible resin substrate.

12. A display using the thin film field effect transistor according to claim 1.