Trench mosfet and manufacturing method thereof

• US 20090127617A1
• Filed: 11/18/2008
• Published: 05/21/2009
• Est. Priority Date: 11/19/2007
• Status: Abandoned Application

• Current Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Original Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Inventors: Shin, Hyun Kwang, Lee, Oh Hyeong
• Application Number:
  US12/292,391
• Publication Number:
  US 20090127617A1
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 21/02233 of the semiconductor substrate or a semiconductor layer
• CPC Class Codes: H01L 21/28556 by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

This invention relates to a trench MOSFET, which can lower parasitic capacitance, thereby increasing a switching speed, and to a method of manufacturing the trench MOSFET. The trench MOSFET includes a substrate having an epi layer and a body layer sequentially formed thereon, a trench formed vertically in the central portion of the epi layer and the body layer, a first gate oxide film formed on the inner wall of the trench, a diffusion oxide film formed in the epi layer between the lower surface of the trench and the upper surface of the substrate to have a thickness greater than a thickness of the first gate oxide film and a width greater than a width of the trench, a gate formed in the trench having the first gate oxide film, a second gate oxide film formed on the gate, and a source region formed at both sides of the upper portion may be of the gate, thus reducing the generation of parasitic capacitance between the epi layer corresponding to a drain region and the gate, thereby improving a switching speed.

Claims

1. A trench MOSFET, comprising:

a substrate, having an epi layer and a body layer sequentially formed thereon;

a trench formed vertically in a central portion of the epi layer and the body layer;

a first gate oxide film formed on an inner wall of the trench;

a diffusion oxide film formed in the epi layer between a lower surface of the trench and an upper surface of the substrate to have a thickness greater than a thickness of the first gate oxide film and a width greater than a width of the trench;

a gate formed in the trench having the first gate oxide film;

a second gate oxide film formed on the gate; and

a source region formed at both sides of an upper portion of the gate.

2. The trench MOSFET as set forth in claim 1, wherein a center of an upper portion of the diffusion oxide film in contact with a lower portion of the gate is formed to have a hollow.

3. The trench MOSFET as set forth in claim 1, wherein the diffusion oxide film has a thickness from 1500 Å

to 4000 Å

.

4. The trench MOSFET as set forth in claim 1 or 3, wherein the diffusion oxide film has a thickness from 2000 Å

to 2500 Å

.

5. The trench MOSFET as set forth in claim 1, further comprising an upper metal formed on the trench MOSFET having the second gate oxide film and the source region.

6. The trench MOSFET as set forth in claim 1, further comprising a high-concentration contact region formed on a portion of the body layer having no source region.

7. The trench MOSFET as set forth in claim 1, wherein the source region is formed on the body layer, and which further comprises a high-concentration contact region formed on a surface of an upper portion of the body layer having no source region.

8. The trench MOSFET as set forth in claim 6 or 7, further comprising an upper metal formed on the trench MOSFET having the second gate oxide film, the source region, and the contact region.

9. The trench MOSFET as set forth in any one of claims 6 to 8, wherein the substrate, the epi layer, and the source region are doped with an N type dopant, the body layer is doped with a P type dopant, and the contact region is doped with a high-concentration P+ type dopant.

10. The trench MOSFET as set forth in any one of claims 6 to 8, wherein the substrate, the epi layer, and the source region are doped with a P type dopant, the body layer is doped with an N type dopant, and the contact region is doped with a high-concentration N+ type dopant.

11. A method of manufacturing a trench MOSFET, comprising:

preparing a substrate having an epi layer and a body layer sequentially formed thereon;

forming a first hard mask for forming a trench on the body layer;

etching a central portion of the body layer and an upper portion of the epi layer using the first hard mask as an etching mask, thus forming the trench;

forming a first gate oxide film and a second hard mask on an inner surface of the trench, etching a bottom of the second hard mask, and then etching the first gate oxide film and the epi layer which are located under the etched second hard mask;

subjecting the etched epi layer to thermal oxidation, thus forming a diffusion oxide film having a thickness greater than a thickness of the first gate oxide film and a width greater than a width of the trench;

forming a gate in the trench having the diffusion oxide film at a lower portion thereof; and

forming a second gate oxide film on the gate, and then forming a source region on the body layer.

12. The method as set forth in claim 11, wherein a center of an upper portion of the diffusion oxide film in contact with a lower portion of the gate is formed to have a hollow.

13. The method as set forth in claim 11, wherein the diffusion oxide film has a thickness from 1500 Å

to 4000 Å

.

14. The method as set forth in claim 11 or 13, wherein the diffusion oxide film has a thickness from 2000 Å

to 2500 Å

.

15. The method as set forth in claim 11, further comprising forming an upper metal on the trench MOSFET having the source region and the second gate oxide film.

16. The method as set forth in claim 11, further comprising forming a high-concentration contact region on a portion of the body layer having no source region.

17. The method as set forth in claim 11, wherein the source region is formed on the body layer, and which further comprises forming a high-concentration contact region on a surface of an upper portion of the body layer having no source region.

18. The method as set forth in claim 16 or 17, further comprising forming an upper metal on the trench MOSFET having the source region, the second gate oxide film, and the contact region.

19. The method as set forth in claim 11, wherein the first hard mask and the second hard mask are a nitride film or an oxide film.

20. The method as set forth in claim 19, wherein the first hard mask and the second hard mask are formed through low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition.

21. The method as set forth in claim 11, wherein the etching the first gate oxide film and the epi layer which are located under the etched second hard mask is performed by etching the first gate oxide film and then etching the epi layer.

22. The method as set forth in claim 11, wherein the etching the first gate oxide film and the epi layer which are located under the etched second hard mask is performed by simultaneously etching the first gate oxide film and the epi layer.

23. The method as set forth in any one of claims 16 to 18, wherein the substrate, the epi layer and the source region are doped with an N type dopant, the body layer is doped with a P type dopant, and the contact region is doped with a high-concentration P+ type dopant.

24. The method as set forth in claim 16 or 18, wherein the substrate, the epi layer, and the source region are doped with a P type dopant, the body layer is doped with an N type dopant, and the contact region is doped with a high-concentration N+ type dopant.