SEMICONDUCTOR DEVICE

• US 20090127625A1
• Filed: 11/20/2008
• Published: 05/21/2009
• Est. Priority Date: 11/21/2007
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: OHGURO, Tatsuya
• Granted Patent: US 8,154,089 B2
• Time in Patent Office: Days
• US Class Current: 257/365
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device according to one embodiment includes: a substrate; a plurality of fins made of a semiconductor and formed on the substrate; a plurality of via contact regions formed between the fins, the plurality of via contact regions and the plurality of the fins constituting a closed loop structure; a gate contact region on the substrate arranged at a position surrounded by the closed loop structure; a plurality of gate electrodes connected to the gate contact region respectively, each of the plurality of gate electrodes sandwiching both side faces of each of the plurality of fins between its opposite regions via gate insulating film; and source/drain regions formed in regions in the plurality of fins and in the contact region, the regions being formed on both sides of a region sandwiched by the gate electrodes along longitudinal direction of the fin.

Claims

1. A semiconductor device, comprising:

a substrate;

a plurality of fins made of a semiconductor and formed on the substrate;

a plurality of via contact regions formed between the fins, the plurality of via contact regions and the plurality of the fins constituting a closed loop structure;

a gate contact region on the substrate arranged at a position surrounded by the closed loop structure;

a plurality of gate electrodes connected to the gate contact region respectively, each of the plurality of gate electrodes sandwiching both side faces of each of the plurality of fins between its opposite regions via gate insulating film; and

source/drain regions formed in regions in the plurality of fins and in the contact region, the regions being formed on both sides of a region sandwiched by the gate electrodes along longitudinal direction of the fin.

2. The semiconductor device according to claim 1, wherein the plurality of fins comprise the multiple closed loop structures connected each other via the contact region;

and

the plurality of gate electrodes are formed so as to respectively correspond to the fins of which number is equal to the number of the closed loop structures.

3. The semiconductor device according to claim 1, wherein the even numbers of the gate electrodes, the contact regions and the fins are formed, respectively.

4. The semiconductor device according to claim 3, wherein four of the gate electrodes and four of the contact regions are formed, and the closed loop structure is tetragonal.

5. The semiconductor device according to claim 2, wherein the even numbers of the gate electrodes, the contact regions and the fins are formed, respectively.

6. The semiconductor device according to claim 5, wherein four of the gate electrodes and four of the contact regions are formed, and the multi closed loop structure is tetragonal.

7. The semiconductor device according to claim 2, wherein the multi closed loop structure is a double closed loop structure.

8. The semiconductor device according to claim 5, wherein the multi closed loop structure is a double closed loop structure.

9. The semiconductor device according to claim 6, wherein the multi closed loop structure is a double closed loop structure.

10. The semiconductor device according to claim 1, wherein the closed loop structure is a regular polygon;

and

the gate contact region is located at a center of the closed loop structure.

11. The semiconductor device according to claim 10, wherein the closed loop structure is a regular hexagon.

12. The semiconductor device according to claim 2, wherein the multi closed loop structure is a regular polygon, and the gate contact region is located at a center of the multi closed loop structure.

13. The semiconductor device according to claim 12, wherein the multi closed loop structure is a regular hexagon.

14. The semiconductor device according to claim 1, wherein a silicide layer is formed on upper portions of the plurality of gate electrodes.

15. The semiconductor device according to claim 1, wherein each of the plurality of the gate electrodes is arranged so as to extend in a direction orthogonal to each of the plurality of the fins from the gate contact region.

16. The semiconductor device according to claim 1, wherein each of the plurality of gate electrodes comprises metal layer and semiconductor layer formed on the metal layer.

17. The semiconductor device according to claim 1, wherein distances between the gate contact region and the plurality of fins are substantially uniform.

18. The semiconductor device according to claim 1, wherein each of the contact regions includes a source/drain region being shared by FinFETs comprising the two fins adjacent to each of the contact regions.

19. The semiconductor device according to claim 1, wherein the gate insulating film is also formed between the upper surface of each of the plurality of fins and each of the plurality of gate electrodes.

20. The semiconductor device according to claim 1, wherein the distances between each of the contact regions and the gate electrodes formed on the fins adjacent to each of the contact regions are substantially uniform.