SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20090127634A1
• Filed: 11/11/2008
• Published: 05/21/2009
• Est. Priority Date: 11/15/2007
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Tsuno, Hitoshi
• Granted Patent: US 8,063,412 B2
• Time in Patent Office: Days
• US Class Current: 257/390
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device includes a semiconductor substrate having an active region, a plurality of gate electrodes formed on the active region with a gate insulating film therebetween, and a dummy pattern formed on the active region in at least a part thereof between the gate electrodes. The dummy pattern is formed so that a spacing between gate electrodes adjacent to each other, and a spacing between the dummy pattern and the gate electrodes adjacent to the dummy pattern, are within predetermined ranges.

Claims

1. A semiconductor device comprising:

a semiconductor substrate having an active region;

a plurality of gate electrodes formed on the active region with a gate insulating film interposed therebetween; and

a dummy pattern formed on the active region in at least a part thereof between the gate electrodes,

wherein the dummy pattern is formed so that a spacing between the gate electrodes adjacent to each other, and a spacing between the dummy pattern and the gate electrodes adjacent to the dummy pattern, are within predetermined ranges.

2. The semiconductor device as claimed in claim 1, wherein the dummy pattern is composed of a part of a sidewall forming film used for forming sidewalls on side faces of the gate electrodes.

3. The semiconductor device as claimed in claim 1, further comprising a stress liner film for applying a stress to the semiconductor substrate to cover the gate electrodes and the dummy pattern.

4. The semiconductor device as claimed in claim 1, wherein diffusion layers formed in the semiconductor substrate at both sides of the dummy pattern are connected to each other via an interconnect.

5. The semiconductor device as claimed in claim 1, wherein the dummy pattern has a slit as deep as reaching the semiconductor substrate.

6. The semiconductor device as claimed in claim 1, wherein the dummy pattern is composed of an insulating film different from the sidewall forming film.

7. A method of manufacturing a semiconductor device comprising the steps of:

forming a plurality of gate electrodes on an active region of a semiconductor substrate with a gate insulating film interposed therebetween;

forming a sidewall forming film on the semiconductor substrate to cover the gate electrodes;

forming an etching mask on the sidewall forming film in at least a part thereof between the gate electrodes; and

forming a dummy pattern on the active region in at least a part thereof between the gate electrodes while forming sidewalls on both side faces of the gate electrodes by etching back the sidewall forming film through the etching mask,

wherein the etching mask is formed so that a spacing between the gate electrodes adjacent to each other, and a spacing between the dummy pattern and the gate electrodes adjacent to the dummy pattern, are within predetermined ranges.

8. A method of manufacturing a semiconductor device comprising:

forming a plurality of gate electrodes on an active region of a semiconductor substrate with a gate insulating film interposed therebetween;

forming a sidewall forming film on the semiconductor substrate to cover the gate electrodes, and then etching back the sidewall forming film to thereby form sidewalls on the side faces of the gate electrodes;

forming an insulating film on the semiconductor substrate having the sidewalls formed thereon;

forming an etching mask on the insulating film in at least a part thereof between the gate electrodes; and

etching the sidewall forming film by using the etching mask, to thereby form a dummy pattern on the active region in at least a part thereof between the gate electrodes,

wherein the etching mask is formed so that a spacing between the gate electrodes adjacent to each other, and a spacing between the dummy pattern and the gate electrodes adjacent to the dummy pattern, are within predetermined ranges.