STACKED SEMICONDUCTOR DEVICE AND METHOD OF FORMING SERIAL PATH THEREOF

• US 20090127668A1
• Filed: 11/19/2008
• Published: 05/21/2009
• Est. Priority Date: 11/21/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Choi, Young-Don
• Granted Patent: US 7,816,776 B2
• Time in Patent Office: Days
• US Class Current: 257/621
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/0615 Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
• CPC Class Codes: H01L 2224/1416 Random layout, i.e. layout with no symmetry
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/14 of a plurality of bump connectors
• CPC Class Codes: H01L 24/17 of a plurality of bump connectors
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/01021 Scandium [Sc]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01058 Cerium [Ce]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/30107 Inductance

Abstract

A stacked semiconductor device and a method of forming a serial path of the stacked semiconductor device are provided. The stacked semiconductor device includes a plurality of chips each having a first internal circuit for receiving an input signal, performing a designated operation and outputting an output signal. Each of the chips includes a serial bump disposed at the same position on one surface of each of the chips, receiving the input signal and transferring the input signal to the first internal circuit, and a serial through-silicon via (TSV) disposed at a position symmetrical to the serial bump with respect to a center of the chip to penetrate the chip, and receiving and transferring the output signal. Here, the chips are alternately rotated and stacked, so that the serial TSV and the serial bumps of adjacent chips contact each other. According to the stacked semiconductor device and method, a plurality of chips having the same pattern are rotated about the center of the chips and stacked, so that a parallel path and a serial path can be formed.

Claims

1. A stacked semiconductor device, comprising:

a plurality of chips each having a first internal circuit configured to receive an input signal, the first internal circuit configured to perform a designated operation and output an output signal, wherein each of the chips includes;

a serial bump disposed at a same position on one surface of each of the chips, configured to receive the input signal, and to transfer the received input signal to the first internal circuit; and

a serial Through-Silicon-Via (TSV), penetrating the chip and disposed at a position symmetrical to the serial bump with respect to a center of the chip and configured to receive and transfer the output signal, wherein the chips are alternately rotated and stacked on one another such that the serial TSV and the serial bumps of adjacent chips contact each other.

2. The stacked semiconductor device according to claim 1, wherein each of the chips further includes:

a second internal circuit for receiving/outputting a first common signal;

a first parallel bump disposed at the same position on the surface of each of the chips, and configured to input/output the first common signal to/from the second internal circuit;

a first parallel TSV disposed at a same position as the first parallel bump to penetrate the chip, and configured to transfer the first common signal;

a second parallel bump disposed at a position symmetrical to the first parallel bump with respect to the center of the chip on one surface of the chip, and configured to input/output the first common signal to/from the second internal circuit; and

a second parallel TSV disposed at a same position as the second parallel bump to penetrate the chip, and transferring the first common signal.

3. The stacked semiconductor device according to claim 2, wherein each of the chips further includes:

a first switch connected between the first parallel bump and the second internal circuit, and configured to select and transfer one of the first common signal and a second common signal to the second internal circuit; and

a second switch connected between the second parallel bump and the second internal circuit, and configured to transfer another of the first common signal and the second common signal to the second internal circuit.

4. The stacked semiconductor device according to claim 3, wherein each of the chips further includes:

a first control bump disposed at the same position on the surface of each of the chips, configured to receive a first control signal to control the first switch to select one of the first and second common signals, and to transfer the received first control signal to the first switch;

a first control TSV disposed at the same position as the first control bump to penetrate the chip, and configured to transfer the first control signal;

a second control bump disposed at a position symmetrical to the first control bump with respect to the center of the chip on one surface of the chip, configured to receive a second control signal for controlling the second switch to select the other of the first and second common signals, and to transfer the received second control signal to the second switch; and

a second control TSV disposed at the same position as the second control bump to penetrate the chip, and configured to transfer the second control signal.

5. The stacked semiconductor device according to claim 4, wherein the first and second switches comprise multiplexers (MUXs).

6. A method of forming a serial path of a stacked semiconductor device including a plurality of chips each having a first internal circuit for receiving an input signal, performing a designated operation and outputting an output signal, the method comprising:

forming a serial bump for receiving the input signal and transferring the received input signal to the first internal circuit at the same position on one surface of each of the chips;

forming a serial through-silicon via (TSV) for receiving the output signal and transferring the output signal at a position symmetrical to the serial bump with respect to a center of each of the chips to penetrate each of the chips; and

alternately rotating and stacking the chips such that the serial TSV and the serial bumps of adjacent chips contact each other.

7. The method according to claim 6, further comprising:

forming a parallel path for simultaneously inputting/outputting a first common signal to/from second internal circuits of the respective chips performing a designated operation.

8. The method according to claim 7, wherein forming the parallel path includes:

forming a first parallel bump for inputting/outputting the first common signal to/from the second internal circuit at the same position on one surface of each of the chips;

forming a first parallel TSV for transferring the first common signal at the same position as the first parallel bump to penetrate each of the chips;

forming a second parallel bump for inputting/outputting the first common signal to/from the second internal circuit at a position symmetrical to the first parallel bump with respect to the center of each of the chips on one surface of each of the chips; and

forming a second parallel TSV for transferring the first common signal at the same position as the second parallel bump to penetrate each of the chips.

9. The method according to claim 8, wherein forming the parallel path further includes:

forming a first switch connected between the first parallel bump and the second internal circuit of each of the chips and selecting and transferring one of the first common signal and a second common signal to the second internal circuit; and

forming a second switch connected between the second parallel bump and the second internal circuit of each of the chips and transferring the other of the first common signal and the second common signal to the second internal circuit.

10. The method according to claim 9, wherein forming the parallel path further includes:

forming a first control bump for transferring a first control signal for controlling the first switch to the first switch at the same position on one surface of each of the chips;

forming a first control TSV for transferring the first control signal at the same position as the first control bump to penetrate each of the chips;

forming a second control bump for receiving a second control signal for controlling the second switch and transferring the received second control signal to the second switch at a position symmetrical to the first control bump with respect to the center of each of the chips on one surface of each of the chips; and

forming a second control TSV for transferring the second control signal at the same position as the second control bump to penetrate each of the chips.