Stacking die package structure for semiconductor devices and method of the same

• US 20090127686A1
• Filed: 11/21/2007
• Published: 05/21/2009
• Est. Priority Date: 11/21/2007
• Status: Abandoned Application

• Current Assignee: Advanced Chip Engineering Technology Inc.
• Original Assignee: Advanced Chip Engineering Technology Inc.
• Inventors: Wang, Chi-Yu, Yang, Wen-Kun, Hsu, Hsien-Wen
• Application Number:
  US11/984,781
• Publication Number:
  US 20090127686A1
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/1035 the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01059 : Praseodymium [Pr]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

The present invention disclosed a first multi-die package structure for semiconductor devices, the structure comprises a substrate having die receiving window and inter-connecting through holes formed therein; a first level semiconductor die formed under a second level semiconductor die by back-to-back scheme and within the die receiving window, wherein the first multi-die package includes first level contact pads formed under the first level semiconductor die having a first level build up layer formed there-under to couple to a first bonding pads of the first level semiconductor die; a second level contact pads formed on the second level semiconductor die having a second level build up layer formed thereon to couple to second bonding pads of the second level semiconductor die; and conductive bumps formed under the first level build up layer.

Claims

1. A first multi-die package structure for semiconductor devices, comprising:

a substrate having die receiving window and inter-connecting through holes formed therein;

a first level semiconductor die formed under a second level semiconductor die by back-to-back scheme and within said die receiving window, wherein said first multi-die package includes first level contact pads formed under said first level semiconductor die having a first level build up layer formed there-under to couple to a first bonding pads of said first level semiconductor die;

a second level contact pads formed on said second level semiconductor die having a second level build up layer formed thereon to couple to second bonding pads of said second level semiconductor die; and

conductive bumps formed under said first level build up layer for coupling to said first level contact pads.

2. The structure of claim 1, wherein said first level build up layer includes a sandwich structure having dielectric/RDL/dielectric.

3. The structure of claim 2, further comprising UBM structure in said first level build up layer for coupling said RDL.

4. The structure of claim 1, wherein said second level build up layer includes a sandwich structure having dielectric/RDL/dielectric.

5. The structure of claim 4, further comprising UBM structure in said second level build up layer for coupling said RDL.

6. The structure of claim 1, further comprising adhesion materials attached between said first and second level semiconductor dice.

7. The structure of claim 1, wherein said first level build up layer coupled to said second build up layer through interconnecting through holes.

8. The structure of claim 1, wherein said first level die is adhered with said second level die by an adhesive material having elastic properties.

9. The structure of claim 8, wherein said adhesive material includes silicon rubber, rubber resin, epoxy resin, polymer resin or the composition thereof.

10. The structure of claim 1, further comprising an isolation base formed over said second level package.

11. The structure of claim 10, wherein said isolation base is formed of epoxy, FR4, FR5, PI, PCB, BT or organic material.

12. The structure of claim 11, wherein said isolation base includes glass fiber contained therein.

13. The structure of claim 1, further comprising core paste material formed adjacent to said first and second level semiconductor dice.

14. The structure of claim 1, further comprising a second multi-die structure formed adjacent to said first multi-die structure.

15. The structure of claim 1, further comprising a third multi-die structure formed on said first multi-die structure.

16. The structure of claim 15, further comprising further conductive bumps connected between said first and said third multi-die structures.

17. A method of forming a multi-die package structure for semiconductor devices, comprising:

applying a second die with active surface on a first tape;

applying a back side of a first die on a second tape;

picking and placing said first die on the back side of said second die having an alignment pattern for fine alignment during placement;

picking said adhered first die and second die from sawed wafer to place onto a die placement tool and sucking said active surface of said second die onto said die placement tool;

aligning a substrate having die receiving window to said adhered first die and second die and adhered on said die placement tool by glue pattern, wherein said substrate includes inter-connecting through holes;

forming core paste material into the gap between the edge of said first die, said second die and the sidewall of said die receiving window;

coating a first lower dielectric layer on the active surface of said first die and exposing first bonding pads and first contact pads of said substrate;

forming a lower RDL to couple to said first bonding pads;

forming a second lower dielectric layer on said lower RDL and exposing first solder contact pads to form a first UBM structure;

releasing glue pattern to separate a panel from said die replacement tool, and followed by cleaning said active surface of said second die;

forming a first upper dielectric layer and expose a second bonding pads of said second die and second contact pads of said substrate;

forming a upper RDL to coupled to said second bonding pads;

forming a second upper dielectric layer and to expose said second solder contact pads to form a second UBM structure.

18. The method of claim 17, further comprising a step of forming an isolation base with adhesion material over said upper RDL and/or said second upper dielectric layer, followed by curing said isolation base.

19. The method of claim 17, further comprising forming using a carrier to support said panel from said die placement tool and protect the lower RDL before forming said first upper dielectric layer.

20. The method of claim 19, further comprising releasing said carrier from said panel, followed by cleaning the surface of lower side, and performing ball placement.

21. The method of claim 17, further comprising aligning and placing a second panel onto said first panel to let ball array contacts with flux of UBM, followed by re-flowing to form interconnection.

22. The method of claim 18, wherein said isolation base is formed of epoxy, FR4, FR5, PI, PCB, BT or organic material.

23. The method of claim 22, wherein said isolation base includes glass fiber contained therein.

24. The method of claim 17, further comprising core paste material formed adjacent to said first and second dice.

25. The method of claim 17, wherein said first die and said second die are adhered by adhesive material that includes silicon rubber, rubber resin, epoxy resin, polymer resin or the composition thereof.