Low Dropout Voltage Regulator

• US 20090128107A1
• Filed: 05/19/2008
• Published: 05/21/2009
• Est. Priority Date: 11/21/2007
• Status: Abandoned Application

• Current Assignee: Vimicro Corporation
• Original Assignee: Vimicro Corporation
• Inventors: YIN, Hang, TIAN, Wenbo, WANG, Zhao
• Application Number:
  US12/122,721
• Publication Number:
  US 20090128107A1
• Time in Patent Office: Days
• US Class Current: 323/280
• CPC Class Codes: G05F 1/575 characterised by the feedback circuit

Abstract

Improved designs of an LDO voltage regulator with ultra low quiescent current are disclosed. According to one embodiment, an LDO voltage regulator is designed to completely cancel an intermediate gain stage while decreasing a quiescent current and to stabilize a loop circuit by means of two zeros introduced in a frequency transfer function thereof. Such a LDO voltage regulator does not increase the power consumption and applicable in many circuits used in electronic devices.

Claims

1. An LDO voltage regulator, comprising:

an unregulated voltage input port;

a regulated voltage output port;

a differential amplifier having a pair of input terminals and an output terminal, one input terminal connected to a reference voltage;

a voltage divider connected between the regulated voltage output port and a ground reference and having a voltage divider node providing a feedback voltage to the other input terminal of the differential amplifier;

an output pass transistor having a control terminal connected to the output terminal of the differential amplifier, an input terminal connected to the unregulated voltage input port and an output terminal;

a compensation resistor connected between the regulated voltage output port and the output terminal of the output pass transistor; and

a compensation capacitor connected between the output terminal of the output pass transistor and the voltage divider node.

2. The LDO voltage regulator according to claim 1, wherein the out pass transistor is a P-type MOS field effect transistor, a gate electrode of the PMOS field effect transistor serves as the control terminal, a source electrode of the PMOS field effect transistor serves as the input terminal and a drain electrode of the PMOS field effect transistor serves as the output terminal.

3. The LDO voltage regulator according to claim 1, further comprising an output capacitor connected between the regulated voltage output port and the ground reference.

4. The LDO voltage regulator according to claim 1, further comprising a load resistor connected between the regulated voltage output port and the ground reference.

5. The LDO voltage regulator according to claim 1, wherein the voltage divider comprises a first ladder resistor and a second ladder resistor connected in series, the voltage divider node is located between the first ladder resistor and the second ladder resistor.

6. The LDO voltage regulator according to claim 2, further comprising another output pass transistor being a P-type MOS field effect transistor, wherein a drain electrode of the another output pass transistor is connected to the regulated voltage output port, a source electrode of the another output pass transistor is connected to the unregulated voltage input port, and a gate electrode of the another output pass transistor is connected to the output terminal of the differential amplifier.

7. The LDO voltage regulator according to claim 6, wherein a current flowing through the output pass transistor is less than a current flowing through the another output pass transistor.

8. The LDO voltage regulator according to claim 1, wherein the differential amplifier comprises a plurality of current mirrors, each branch of the current mirrors adopts two stage cascade connection of NMOS transistors or PMOS transistors.

9. An LDO voltage regulator, comprising:

an unregulated voltage input port;

a regulated voltage output port;

a differential amplifier having a pair of input terminals and an output terminal, one input terminal connected to a reference voltage;

a voltage divider connected between the regulated voltage output port and a ground reference and having a voltage divider node providing a feedback voltage to the other input terminal of the differential amplifier;

a first output pass transistor having a control terminal connected to the output terminal of the differential amplifier, an input terminal connected to the unregulated voltage input port and an output terminal;

a second output pass transistor having a control terminal connected to the output terminal of the differential amplifier, an input terminal connected to the unregulated voltage input port and an output terminal connected to the regulated voltage output port;

a compensation resistor connected between the regulated voltage output port and the output terminal of the first output pass transistor;

a compensation capacitor connected between the output terminal of the first output pass transistor and the voltage divider node.

10. The LDO voltage regulator according to claim 9, wherein the pass transistors both are P-type MOS field effect transistors, a gate electrode of the MOS field effect transistor serves as the control terminal, a source electrode of the MOS field effect transistor serves as the input terminal, and a drain electrode of the MOS field effect transistor serves as the output terminal.

11. The LDO voltage regulator according to claim 9, wherein a current flowing through the first output pass transistor is less than a current flowing through the second output pass transistor.

12. The LDO voltage regulator according to claim 9, further comprising an output capacitor and a load resistor connected in parallel between the regulated voltage output port and the ground reference.

13. The LDO voltage regulator according to claim 9, wherein the ratio of width to length of the first pass transistor is O, the ratio of width to length of the second pass transistor is P, the ratio of O to P is within 1/10000˜

1/10.

14. The LDO voltage regulator according to claim 12, wherein the LDO voltage regulator has three poles and two zeros within bandwidth, two of the three poles are cancelled by corresponding zeros and another pole is designed to be a domain pole, and wherein one of the two zeros is formed by the output capacitor and the compensation resistor.

15. The LDO voltage regulator according to claim 9, wherein the differential amplifier comprises a plurality of current mirrors, each branch of the current mirrors adopts two stage cascade connection of NMOS transistors or PMOS transistors.

16. An LDO voltage regulator, comprising:

first and second output pass transistors having a common gate electrode receiving a control signal, a common source electrode connected to an unregulated voltage input port, an output current of the fist output pass transistor less than an output current of the second output pass transistor, a drain electrode of the second output pass transistor connected to a regulated voltage output port;

a compensation resistor connected between the regulated voltage output port and a drain electrode of the first output pass transistor;

a compensation capacitor connected between the drain terminal of the first output pass transistor and a voltage feedback node.