DUAL SENSOR SYSTEM HAVING FAULT DETECTION CAPABILITY

• US 20090128160A1
• Filed: 11/19/2007
• Published: 05/21/2009
• Est. Priority Date: 11/19/2007
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Chiaburu, Liviu, Fuhrman, Marco, Ohe, Tom D.
• Granted Patent: US 7,855,562 B2
• Time in Patent Office: Days
• US Class Current: 324/537
• CPC Class Codes: G01D 3/08 with provision for safeguarding the apparatus, e.g. against abnormal operation, against breakdown
• CPC Class Codes: G01L 27/007 Malfunction diagnosis, i.e. diagnosing a sensor defect

Abstract

A sensor system (20) includes transducers (32, 34) each yielding an analog signal (37, 39) representing a parameter independently sensed by each of the transducers (32, 34). The signals (37, 39) are summed and the resulting transducer signal (46) is converted to a digital transducer signal (26) by a high resolution analog-to-digital converter (ADC) (48). Concurrently, one of the signals (37, 39) is subtracted from the other. The resulting difference signal (56) is converted to a digital difference signal (60) by a low resolution ADC (58). When the digital difference signal (60) is within a threshold window (78), a fault signal (28) indicates a normal condition (80) of the transducers (32, 34). When the signal (60) falls outside of the threshold window (78), a fault signal (28) indicates a fault condition (82) of the transducers. The transducer and fault signals (26, 28) are concurrently output from the sensor system (20).

Claims

1. A sensor system having fault detection capability comprising:

a first transducer producing a first analog signal;

a second transducer producing a second analog signal, said first and second analog signals representing a parameter being independently sensed by both of said first and second transducers;

a subtraction circuit in communication with each of said first and second transducers for determining a difference between said first analog signal and said second analog signal to produce a difference signal; and

an analog-to-digital converter (ADC) in communication with said subtraction circuit for receiving said difference signal and generating a corresponding digital difference signal indicative of a condition of said first and second transducers.

2. A sensor system as claimed in claim 1 further comprising a processor in communication with said ADC, said processor comparing said digital difference signal against a threshold value to determine whether said condition of said first and second transducers is one of a normal condition and a fault condition.

3. A sensor system as claimed in claim 2 wherein said processor outputs a first logical output signal in response to determination of said normal condition and said processor outputs a second logical output signal in response to determination of said fault condition.

4. A sensor system as claimed in claim 2 wherein said threshold value is a threshold window around a normative value for said difference signal, and said processor compares said difference signal against said threshold window and flags said difference signal as said fault condition when said difference signal falls outside of said threshold window.

5. A sensor system as claimed in claim 1 further comprising a summing circuit in communication with each of said first and second transducers for adding said first analog signal and said second analog signal to produce a transducer output signal.

6. A sensor system as claimed in claim 5 wherein said ADC is a first ADC, and said sensor system further comprises a second ADC in communication with said summing circuit, said second ADC receiving said transducer output signal and generating a digital transducer output signal indicative of said sensed parameter.

7. A sensor system as claimed in claim 6 wherein said first ADC exhibits a first resolution, said second ADC exhibits a second resolution, said second resolution being greater than said first resolution.

8. A sensor system as claimed in claim 6 wherein further comprising:

a processor in communication with said first ADC for generating a logical output signal in response to said digital difference signal indicative of said condition of said first and second transducers; and

an output in communication with each of said processor and said second ADC for concurrent provision of said logical output signal with said transducer output signal.

9. A sensor system as claimed in claim 1 wherein said first and second transducers are microelectromechanical sensors.

10. A method of fault detection in a device that includes a dual sensor system having first and second transducers that independently sense a parameter, said method comprising:

producing a first analog signal at said first transducer;

producing a second analog signal at said second transducer, said first and second analog signals representing said sensed parameter;

subtracting said first analog signal from said second analog signal to produce a difference signal;

converting said difference signal to a digital difference signal indicative of a condition of said first and second transducers;

comparing said digital difference signal against a threshold value to determine whether said condition of said first and second transducers is one of a normal condition and a fault condition; and

providing a logical output signal responsive to said digital difference signal to a downstream component of said device to inform said downstream component of said condition of said first and second transducers.

11. A method as claimed in claim 10 further comprising:

summing said first and second analog signals to produce a transducer output signal;

converting said transducer output signal to a digital transducer output signal; and

providing said digital transducer output signal to said downstream component concurrent with communication of said logical output signal to said downstream component.

12. A method as claimed in claim 11 further comprising:

utilizing a first analog-to-digital converter (ADC) to convert said difference signal to said digital difference signal, said ADC being characterized by a first resolution; and

utilizing a second ADC to convert said transducer output signal to said digital transducer output signal, said second ADC being characterized by a second resolution, said second resolution being greater than said first resolution.

13. A device comprising:

a sensor system having fault detection capability, said sensor system including;

a first transducer producing a first analog signal;

a second transducer producing a second analog signal, said first and second analog signals representing a parameter being independently sensed by both of said first and second transducers;

a subtraction circuit in communication with each of said first and second transducers for determining a difference between said first and second analog signals to produce a difference signal;

a summing circuit in communication with each of said first and second transducers for adding said first analog signal and said second analog signal to produce an analog transducer signal;

a first analog-to-digital converter (ADC) in communication with said subtraction circuit for generating a digital difference signal indicative of a condition of said first and second transducers from said analog difference signal, said first ADC being characterized by a first resolution; and

a second ADC in communication with said summing circuit for generating a digital transducer output signal from said analog transducer signal, said second ADC being characterized by a second resolution, said second resolution being greater than said first resolution; and

a downstream component in communication with said sensor system for receiving said digital transducer output signal and a signal indicative of said digital difference signal.

14. A device as claimed in claim 13 further comprising a processor in communication with said ADC, said processor comparing said digital difference signal against a threshold value to determine whether said condition of said first and second transducers is one of a normal condition and a fault condition.

15. A device as claimed in claim 14 wherein said processor outputs a first logical output signal in response to determination of said normal condition and said processor outputs a second logical output signal in response to determination of said fault condition, said signal received by said downstream component being one of said first and second logical output signals.

16. A device as claimed in claim 13 wherein said sensor system further comprises an output interposed between said first and second ADCs and said downstream component for concurrent provision of said transducer output signal with said signal indicative of said digital difference signal.

17. A device as claimed in claim 13 wherein said first and second transducers are microelectromechanical sensors.