Pad invariant FPGA and ASIC devices

• US 20090128188A1
• Filed: 11/19/2007
• Published: 05/21/2009
• Est. Priority Date: 11/19/2007
• Status: Active Grant

• Current Assignee: Callahan Cellular LLC (Intellectual Ventures LLC)
• Original Assignee: Raminda Udaya Madurawe
• Inventors: Madurawe, Raminda Udaya
• Granted Patent: US 7,812,458 B2
• Time in Patent Office: Days
• US Class Current: 326/39
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

A three dimensional semiconductor device, comprising: a plurality of circuit blocks including programmable logic blocks having predetermined positions within the device; a plurality of pads having predetermined positions within the device; and a configuration memory circuit coupled to the programmable logic blocks having a plurality of fabricating methods without altering the predetermined positions of the pads and the circuit blocks.

Claims

1. A semiconductor device, comprising:

a plurality of pads having first predetermined positions;

a first layer including a plurality of circuit blocks having second predetermined positions, at least one of said circuit blocks coupled to one of said pads; and

a second layer positioned above or below the first layer including a memory array coupled to one or more of said circuit blocks, wherein the second layer comprises a plurality of configurations without altering the first and second predetermined positions of pads and circuit blocks, respectively.

2. The device of claim 1, wherein the circuit blocks include programmable logic circuits and the memory array comprises memory elements, at least one of the memory elements is coupled to one programmable logic circuit to configure the programmable logic circuit.

3. The device of claim 1, wherein a said memory array configuration comprises a field programmable memory array to form an FPGA.

4. The device of claim 1, wherein a said memory array configuration comprises a mask programmable metal pattern to form an ASIC.

5. The device of claim 1, wherein one pad is coupled to power or ground supply voltage.

6. The device of claim 1, wherein one pad is coupled to an Input/Output (I/O) circuit block in the first layer, the I/O having an I/O characteristic invariant to memory array configurations.

7. The device of claim 1, wherein the pads are coupled to leads of a package.

8. The device of claim 1, wherein the first layer includes one or more input buffers to receive data from one or more of said pads to program the memory array in a said memory array configuration.

9. The device of claim 1, wherein a said memory array configuration comprises one or more of:

fuses, antifuses, SRAM cells, DRAM cells, metal optional links, EPROMs, EEPROMs, flash, resistance modulating elements, magneto-electric elements, photo-electric elements and ferro-electric elements.

10. The device of claim 1, wherein the first layer comprises circuits to request configuration data from an external storage device for a said memory array configuration.

11. A method for fabricating a 3D device, comprising:

forming a plurality of pads with predetermined positions;

forming a first layer having a plurality of circuit blocks within the predetermined positions, at least one pad is coupled to one circuit block; and

forming a second layer having a plurality of configurations above or below the first layer, the second layer including a memory array coupled to one or more of said circuit blocks.

12. The method of claim 11, wherein forming the second layer includes coupling a memory element in the memory array to one or more programmable logic elements in a said circuit block to configure the circuit block.

13. The method of claim 11, wherein the predetermined positions of the first layer circuit blocks and the plurality of pads are invariant to second layer configurations, and wherein:

in an FPGA configuration, forming the memory array with field programmable memory elements; and

in an ASIC configuration, replacing the memory array with a mask programmable metal pattern prior to fabrication.

14. The method of claim 13, wherein in the FPGA configuration, the mask programmable metal pattern is replaced by the programmable memory array.

15. The method of claim 13, wherein in the ASIC configuration, the metal pattern replicates a predetermined memory pattern for the memory array.

16. The method of claim 11, wherein forming the first layer includes forming a driver circuit to program the memory array from data received by at least one of said pads.

17. The method of claim 13, wherein forming the FPGA comprises depositing thin film transistors on the second layer to construct field programmable memory elements.

18. The method of claim 11, comprising depositing the first and second layers above a semiconductor substrate.

19. A three dimensional semiconductor device, comprising:

a plurality of circuit blocks including programmable logic blocks having predetermined positions within the device;

a plurality of pads surrounding the circuit blocks; and

a configuration memory circuit coupled to the programmable logic blocks having a plurality of fabrication configurations, each configuration fabricated without altering the predetermined positions of the circuit blocks and pads.

20. The device in claim 19, wherein:

a first fabricating configuration comprises a user programmable memory array, and

a second fabricating configuration comprises a mask programmable memory array in lieu of the user programmable memory array.