Pad invariant FPGA and ASIC devices
First Claim
Patent Images
1. A semiconductor device, comprising:
- a plurality of pads having first predetermined positions;
a first layer including a plurality of circuit blocks having second predetermined positions, at least one of said circuit blocks coupled to one of said pads; and
a second layer positioned above or below the first layer including a memory array coupled to one or more of said circuit blocks, wherein the second layer comprises a plurality of configurations without altering the first and second predetermined positions of pads and circuit blocks, respectively.
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Abstract
A three dimensional semiconductor device, comprising: a plurality of circuit blocks including programmable logic blocks having predetermined positions within the device; a plurality of pads having predetermined positions within the device; and a configuration memory circuit coupled to the programmable logic blocks having a plurality of fabricating methods without altering the predetermined positions of the pads and the circuit blocks.
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Citations
20 Claims
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1. A semiconductor device, comprising:
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a plurality of pads having first predetermined positions; a first layer including a plurality of circuit blocks having second predetermined positions, at least one of said circuit blocks coupled to one of said pads; and a second layer positioned above or below the first layer including a memory array coupled to one or more of said circuit blocks, wherein the second layer comprises a plurality of configurations without altering the first and second predetermined positions of pads and circuit blocks, respectively. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method for fabricating a 3D device, comprising:
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forming a plurality of pads with predetermined positions; forming a first layer having a plurality of circuit blocks within the predetermined positions, at least one pad is coupled to one circuit block; and forming a second layer having a plurality of configurations above or below the first layer, the second layer including a memory array coupled to one or more of said circuit blocks. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
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19. A three dimensional semiconductor device, comprising:
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a plurality of circuit blocks including programmable logic blocks having predetermined positions within the device; a plurality of pads surrounding the circuit blocks; and a configuration memory circuit coupled to the programmable logic blocks having a plurality of fabrication configurations, each configuration fabricated without altering the predetermined positions of the circuit blocks and pads. - View Dependent Claims (20)
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Specification