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Pad invariant FPGA and ASIC devices

  • US 20090128188A1
  • Filed: 11/19/2007
  • Published: 05/21/2009
  • Est. Priority Date: 11/19/2007
  • Status: Active Grant
First Claim
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1. A semiconductor device, comprising:

  • a plurality of pads having first predetermined positions;

    a first layer including a plurality of circuit blocks having second predetermined positions, at least one of said circuit blocks coupled to one of said pads; and

    a second layer positioned above or below the first layer including a memory array coupled to one or more of said circuit blocks, wherein the second layer comprises a plurality of configurations without altering the first and second predetermined positions of pads and circuit blocks, respectively.

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