Three dimensional programmable devices
First Claim
1. A three dimensional programmable logic device (PLD), comprising:
- a programmable logic block having a plurality of configurable elements positioned in the logic block in a predetermined layout geometry; and
a first array of configuration memory cells, each of said memory cells coupled to one or more of said configurable elements to program the logic block to a user specification, wherein the first array conforms substantially to the predetermined layout geometry and the first array is positioned substantially above or below the logic block.
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Abstract
In a first aspect, a three dimensional programmable logic device (PLD) comprises a plurality of distributed programmable elements located in a substrate region; and a contiguous array of configuration memory cells, a plurality of said memory cells coupled to the plurality of programmable elements to configure the programmable elements, wherein: the memory array is positioned substantially above or below the substrate region; and the memory array and the substrate region layout geometries are substantially similar. In a second aspect, the 3D PLD comprises a contiguous array of metal cells, each metal cell having the configuration memory cell dimensions and a metal stub coupled to a said configuration memory cell and to one or more of said programmable elements.
345 Citations
23 Claims
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1. A three dimensional programmable logic device (PLD), comprising:
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a programmable logic block having a plurality of configurable elements positioned in the logic block in a predetermined layout geometry; and a first array of configuration memory cells, each of said memory cells coupled to one or more of said configurable elements to program the logic block to a user specification, wherein the first array conforms substantially to the predetermined layout geometry and the first array is positioned substantially above or below the logic block. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A three dimensional programmable logic device (PLD), comprising:
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a plurality of I/O cells, each I/O cell comprising;
a fixed circuit region; and
a programmable circuit region having a plurality of programmable elements to configure the I/O cell; andone or more intellectual property (IP) cores, each IP core comprising;
a fixed circuit region; anda programmable circuit region having a plurality of programmable elements to configure the IP core; and a programmable logic block array region comprising;
a plurality of substantially identical programmable logic blocks replicated to form the array, each said logic block further comprising a plurality of programmable elements; anda programmable region comprising positioned programmable elements of said programmable logic block array region, the one or more of IP core programmable circuit regions and the one or more of I/O cell programmable circuit regions; and a configuration memory array comprising configuration memory cells coupled to one or more of said programmable elements in the programmable region, the memory array programming the programmable region, wherein; the memory array is positioned substantially above or below the programmable region; and the memory array and programmable region layout geometries are substantially identical. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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18. A three dimensional programmable logic device (PLD), comprising:
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a plurality of distributed programmable elements located in a substrate region; and a contiguous array of configuration memory cells, a plurality of said memory cells coupled to the plurality of programmable elements to configure the programmable elements, wherein; the memory array is positioned substantially above or below the substrate region; and the memory array and the substrate region layout geometries are substantially similar. - View Dependent Claims (19, 20, 21, 22, 23)
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Specification