Time delay apparatus

• US 20090128204A1
• Filed: 04/18/2006
• Published: 05/21/2009
• Est. Priority Date: 04/18/2005
• Status: Active Grant

• Current Assignee: Agency For Science Technology and Research
• Original Assignee: Agency For Science Technology and Research
• Inventors: Yin, Jee Khoi, Lim, Teck Hwee, Chia, Yan Wah Michael
• Granted Patent: US 7,956,657 B2
• Time in Patent Office: Days
• US Class Current: 327/157
• CPC Class Codes: H01Q 3/30 varying the relative phase between the radiating elements of an array H01Q3/2605, H01Q3/2658, H01Q3/2682, H01Q3/44 take precedence
• CPC Class Codes: H01Q 3/38 the phase-shifters being digital
• CPC Class Codes: H03L 7/0805 the loop being adapted to provide an additional control signal for use outside the loop
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence

Abstract

A time delay apparatus for generating a plurality of phase shifted signals is described comprising a phase tuner generating a phase control signal and a phase interpolator receiving at least one digital signal and generating the plurality of phase shifted signals by. phase shifting the digital signal according to the phase control signal.

Claims

1. A time delay apparatus for generating a plurality of phase shifted signals comprising

a phase tuner generating a phase control signal and

a phase interpolator receiving at least one digital signal and generating the plurality of phase shifted signals by phase shifting the digital signal according to the phase control signal.

2. The time delay apparatus according to claim 1, wherein the phase tuner is a phase locked loop.

3. The time delay apparatus according to claim 2, wherein the phase locked loop comprises a voltage controlled oscillator and wherein the voltage input to the voltage controlled oscillator for controlling the frequency of the oscillation output by the voltage controlled oscillator is the phase control signal.

4. The time delay apparatus according to claim 3, wherein the voltage controlled oscillator generates a first clock signal and the phase locked loop further comprises

a receiving means for receiving a second clock signal

a phase comparator for comparing the phase difference between the first clock signal and the second clock signal to produce a digital error signal

a charge pump for converting the digital error signal to an analog error signal

a low pass filter for filtering the analog error signal to produce the phase control signal

a frequency divider for dividing the first clock signal.

5. The time delay apparatus according to claim 4, wherein the digital error signal is a digital error pulse signal.

6. The time delay apparatus according to claim 4, wherein the analog error signal is an analog error current.

7. The time delay apparatus according to claim 4, wherein the phase control signal specifies a phase difference and wherein the phase difference is programmable by setting a factor by which the frequency divider divides the first clock signal.

8. The time delay apparatus according to claim 1, further comprising a buffer for buffering the plurality of phase shifted signals.

9. The time delay apparatus according to claim 1 further comprising a comparator receiving at least one wave signal and generating the at least one digital signal by shaping the at least one wave signal.

10. The time delay apparatus according to claim 9, wherein the comparator is an analog to digital converter.

11. The time delay apparatus according to claim 1, wherein the phase control signal specifies a phase difference and each phase shifted signal of the plurality of phase shifted signals is generated by the phase interpolator by phase shifting the digital signal according to multiple of the phase difference.

12. The time delay apparatus according to claim 1, wherein the digital signal is random.

13. The time delay apparatus according to claim 1, wherein the digital signal is pseudo-randomly generated.

15. The time delay apparatus according to claim 5, wherein the analog error signal is an analog error current.

16. The time delay apparatus according to claim 5, wherein the phase control signal specifies a phase difference and wherein the phase difference is programmable by setting a factor by which the frequency divider divides the first clock signal.

17. The time delay apparatus according to claim 6, wherein the phase control signal specifies a phase difference and wherein the phase difference is programmable by setting a factor by which the frequency divider divides the first clock signal.

14. A time delay apparatus for generating a plurality of phase shifted signals comprising

a comparator receiving at least one wave signal and generating at least one digital signal by shaping the at least one wave signal

a phase tuner generating a phase control signal and

a phase interpolator receiving the at least one digital signal and generating the plurality of phase shifted signals by phase shifting the digital signal according to the phase control signal.